On Fri, 7 Apr 2023, Xu Yilun wrote:
> On 2023-04-05 at 11:01:52 +0300, Ilpo Järvinen wrote:
> > On some MAX 10 cards, the BMC firmware is not available to service
> > handshake registers during secure update erase and write phases at
> > normal speeds. This problem affects at least hwmon driver. When the MAX
> > 10 hwmon driver tries to read the sensor values during a secure update,
> > the reads are slowed down (e.g., reading all D5005 sensors takes ~24s
> > which is magnitudes worse than the normal <0.02s).
> >
> > Manage access to the handshake registers using a rw semaphore and a FW
> > state variable to prevent accesses during those secure update phases
> > and return -EBUSY instead.
> >
> > Co-developed-by: Russ Weight <russell.h.weight@xxxxxxxxx>
> > Signed-off-by: Russ Weight <russell.h.weight@xxxxxxxxx>
> > Co-developed-by: Xu Yilun <yilun.xu@xxxxxxxxx>
> > Signed-off-by: Xu Yilun <yilun.xu@xxxxxxxxx>
> > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
> > ---
> > drivers/fpga/intel-m10-bmc-sec-update.c | 17 +++++--
> > drivers/mfd/intel-m10-bmc-core.c | 63 ++++++++++++++++++++++++-
> > drivers/mfd/intel-m10-bmc-pmci.c | 4 ++
> > drivers/mfd/intel-m10-bmc-spi.c | 14 ++++++
> > include/linux/mfd/intel-m10-bmc.h | 27 +++++++++++
> > 5 files changed, 120 insertions(+), 5 deletions(-)
> >
>
> [...]
>
> >
> > +void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state)
> > +{
> > + down_write(&m10bmc->bmcfw_lock);
> > + m10bmc->bmcfw_state = new_state;
> > + up_write(&m10bmc->bmcfw_lock);
>
> Could we also skip this if no handshake is possible like for PMCI?
Did you mean guarding it with !m10bmc->info->handshake_sys_reg_nranges ?
If yes, it's doable (+ I'd add comment mentioning it since it's slightly
trappy to not always have that state updated).
--
i.
