On Wed, Mar 22, 2023 at 10:35:47AM -0400, Tianfei Zhang wrote: > Adding a DFL (Device Feature List) device driver of ToD device for > Intel FPGA cards. > > The Intel FPGA Time of Day(ToD) IP within the FPGA DFL bus is exposed > as PTP Hardware clock(PHC) device to the Linux PTP stack to synchronize > the system clock to its ToD information using phc2sys utility of the > Linux PTP stack. The DFL is a hardware List within FPGA, which defines > a linked list of feature headers within the device MMIO space to provide > an extensible way of adding subdevice features. ... > + dt->ptp_clock = ptp_clock_register(&dt->ptp_clock_ops, dev); > + if (IS_ERR_OR_NULL(dt->ptp_clock)) > + return dev_err_probe(dt->dev, PTR_ERR_OR_ZERO(dt->ptp_clock), > + "Unable to register PTP clock\n"); > + > + return 0; Can be as simple as: ret = PTR_ERR_OR_ZERO(dt->ptp_clock); return dev_err_probe(dt->dev, ret, "Unable to register PTP clock\n"); -- With Best Regards, Andy Shevchenko
