On Fri, Feb 17, 2023 at 04:40:19PM +0000, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > The system controller "shares" a SPI flash device with a QSPI controller > in the MSS. This flash is used to store FPGA bitstreams & other > metadata. IAP and Auto Upgrade both write images to this flash that the > System Controller will use to re-program the FPGA. > > Add a phandle property signifying which flash device is connected to the > system controller. > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > .../soc/microchip/microchip,mpfs-sys-controller.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > index 04ffee3a7c59..97a7cb74cbf9 100644 > --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > @@ -26,6 +26,16 @@ properties: > compatible: > const: microchip,mpfs-sys-controller > > + microchip,bitstream-flash: > + $ref: "/schemas/types.yaml#/definitions/phandle" Drop quotes. With that, Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > + description: > + The SPI flash connected to the system controller's QSPI controller. > + The system controller may retrieve FPGA bitstreams from this flash to > + perform In-Application Programming (IAP) or during device initialisation > + for Auto Update. The MSS and system controller have separate QSPI > + controllers and this flash is connected to both. Software running in the > + MSS can write bitstreams to the flash. > + > required: > - compatible > - mboxes > -- > 2.39.1 >
