On 2022-10-13 at 14:35:55 +0530, Nava kishore Manne wrote:
> Adds PM API for performing Programmable Logic(PL) configuration
> register readback. It provides an interface to the firmware(pmufw)
> to readback the FPGA configuration register.
>
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@xxxxxxx>
> ---
> hanges for v2:
> - None.
>
> Changes for v3:
> - Updated API and config reg read-back handling logic
> - Updated the commit msg to align with the changes.
>
> drivers/firmware/xilinx/zynqmp.c | 35 ++++++++++++++++++++++++++++
> include/linux/firmware/xlnx-zynqmp.h | 11 +++++++++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index d1f652802181..045a113434c2 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -941,6 +941,41 @@ int zynqmp_pm_fpga_get_status(u32 *value)
> }
> EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);
>
> +/**
> + * zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status.
> + * @value: Buffer to store FPGA configuration status.
> + *
> + * This function provides access to the pmufw to get the FPGA configuration
> + * status
> + *
> + * Return: Returns status, either success or error+reason
As mentioned before, please at least specify what value is success
> + */
> +int zynqmp_pm_fpga_get_config_status(u32 *value)
> +{
> + u32 ret_payload[PAYLOAD_ARG_CNT];
> + u32 buf, phys_lower_addr, phys_upper_addr, addr;
reverse santa tree, please
> + int ret;
> +
> + if (!value)
> + return -EINVAL;
> +
> + addr = (u64)&buf;
> +
> + phys_lower_addr = lower_32_bits(addr);
> + phys_upper_addr = upper_32_bits(addr);
u64 addr???
> +
> + ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,
> + XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,
> + phys_lower_addr, phys_upper_addr,
> + XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,
> + ret_payload);
> +
> + *value = ret_payload[1];
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);
> +
> /**
> * zynqmp_pm_pinctrl_request - Request Pin from firmware
> * @pin: Pin number to request
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 9f50dacbf7d6..34b0a9171293 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -70,6 +70,10 @@
> #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
> #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
>
> +/* FPGA Status Reg */
> +#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
> +#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
> +
> /*
> * Node IDs for the Error Events.
> */
> @@ -117,6 +121,7 @@ enum pm_api_id {
> PM_CLOCK_GETRATE = 42,
> PM_CLOCK_SETPARENT = 43,
> PM_CLOCK_GETPARENT = 44,
> + PM_FPGA_READ = 46,
> PM_SECURE_AES = 47,
> PM_FEATURE_CHECK = 63,
> };
> @@ -475,6 +480,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
> int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
> int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
> int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
> +int zynqmp_pm_fpga_get_config_status(u32 *value);
> #else
> static inline int zynqmp_pm_get_api_version(u32 *version)
> {
> @@ -745,6 +751,11 @@ static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
> {
> return -ENODEV;
> }
> +
> +int zynqmp_pm_fpga_get_config_status(u32 *value)
> +{
> + return -ENODEV;
> +}
> #endif
>
> #endif /* __FIRMWARE_ZYNQMP_H__ */
> --
> 2.25.1
>
