Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the programmable logic (PL) through the AXI port.This AXI port helps to establish the data path between the PS and PL. In-order to establish the proper communication data path between PS and PL the AXI port data path should be configured with the proper Bus-width values and it will also handle the PS-PL reset signals to reset the PL domain. This patch series adds afi config drivers support to handle the PS-PL resets and AXI port bus-width configurations. Nava kishore Manne (4): firmware: xilinx: Add afi ioctl support bindings: fpga: Add binding doc for the zynqmp afi config driver bindings: firmware: Update binding doc for the zynqmp afi config node fpga: zynqmp: Add afi config driver .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 + .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml | 100 +++++++++ MAINTAINERS | 6 + drivers/firmware/xilinx/zynqmp.c | 14 ++ drivers/fpga/Kconfig | 13 ++ drivers/fpga/Makefile | 1 + drivers/fpga/zynqmp-afi.c | 211 ++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 36 +++ 8 files changed, 388 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml create mode 100644 drivers/fpga/zynqmp-afi.c -- 2.25.1
