On 2022-08-17 at 17:37:46 -0400, Peter Colberg wrote: > Add a Device Feature List (DFL) feature id for the configurable > IOPLL user clock source, which can be used to configure the clock > speeds that are used for RTL logic that is programmed into the > Partial Reconfiguration (PR) region of an FPGA. Why not use linux clock framework for this IOPLL? And let the PR driver set it togeter with the RTL logic reporgramming? Thanks, Yilun > > The DFL feature id table can be found at: > https://github.com/OPAE/dfl-feature-id > > Signed-off-by: Peter Colberg <peter.colberg@xxxxxxxxx> > --- > drivers/uio/uio_dfl.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/uio/uio_dfl.c b/drivers/uio/uio_dfl.c > index 8f39cc8bb034..69e93f3e7faf 100644 > --- a/drivers/uio/uio_dfl.c > +++ b/drivers/uio/uio_dfl.c > @@ -46,10 +46,12 @@ static int uio_dfl_probe(struct dfl_device *ddev) > > #define FME_FEATURE_ID_ETH_GROUP 0x10 > #define FME_FEATURE_ID_HSSI_SUBSYS 0x15 > +#define PORT_FEATURE_ID_IOPLL_USRCLK 0x14 > > static const struct dfl_device_id uio_dfl_ids[] = { > { FME_ID, FME_FEATURE_ID_ETH_GROUP }, > { FME_ID, FME_FEATURE_ID_HSSI_SUBSYS }, > + { PORT_ID, PORT_FEATURE_ID_IOPLL_USRCLK }, > { } > }; > MODULE_DEVICE_TABLE(dfl, uio_dfl_ids); > -- > 2.28.0 >
