> -----Original Message----- > From: matthew.gerlach@xxxxxxxxxxxxxxx <matthew.gerlach@xxxxxxxxxxxxxxx> > Sent: Tuesday, March 22, 2022 7:05 AM > To: Zhang, Tianfei <tianfei.zhang@xxxxxxxxx> > Cc: Wu, Hao <hao.wu@xxxxxxxxx>; trix@xxxxxxxxxx; mdf@xxxxxxxxxx; Xu, Yilun > <yilun.xu@xxxxxxxxx>; linux-fpga@xxxxxxxxxxxxxxx; linux-doc@xxxxxxxxxxxxxxx; > rdunlap@xxxxxxxxxxxxx; corbet@xxxxxxx > Subject: Re: [PATCH v4 2/2] Documentation: fpga: dfl: add description of > Feature ID > > > > On Thu, 17 Mar 2022, Tianfei Zhang wrote: > > > From: Tianfei zhang <tianfei.zhang@xxxxxxxxx> > > > > This patch adds the description and registration of Feature ID in > > documentation. > > > > Signed-off-by: Tianfei zhang <tianfei.zhang@xxxxxxxxx> > > --- > > Documentation/fpga/dfl.rst | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > > index ef9eec71f6f3..260cac3b7215 100644 > > --- a/Documentation/fpga/dfl.rst > > +++ b/Documentation/fpga/dfl.rst > > @@ -502,6 +502,16 @@ Developer only needs to provide a sub feature driver > with matched feature id. > > FME Partial Reconfiguration Sub Feature driver (see > > drivers/fpga/dfl-fme-pr.c) could be a reference. > > > > +Individual DFL drivers are bound DFL devices based on Feature Type and > Feature ID. > > +The definition of Feature Type and Feature ID can be found: > > + > > +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature- > > +ids.rst > > + > > +If you want to add a new feature ID for FPGA DFL feature device, you > > +must use a pull > > s/you muse use/submit/ Thanks, I will change to: you must submit a pull request ... > > > +request to register a feature ID for DFL. Here is the DFL Feature ID Registry: > > + > > +https://github.com/OPAE/linux-dfl-feature-id > > + > > Location of DFLs on a PCI Device > > ================================ > > The original method for finding a DFL on a PCI device assumed the > > start of the > > -- > > 2.26.2 > > > >
