> Subject: Re: [PATCH] fpga: altera-cvp: Increase the credit timeout > > On Mon, Feb 21, 2022 at 10:11:27PM +0800, tien.sung.ang@xxxxxxxxx wrote: > > From: Ang Tien Sung <tien.sung.ang@xxxxxxxxx> > > > > Increase the timeout for SDM (Secure device manager) data credits from > > 20ms to 40ms. Internal stress tests running at 500 loops failed with the > > current timeout of 20ms. At the start of a FPGA configuration, the CVP > > host driver reads the transmit credits from SDM. It then sends bitstream > > FPGA data to SDM based on the total credits. Each credit allows the > > CVP host driver to send 4kBytes of data. There are situations whereby, > > the SDM did not respond in time during testing. Why this timeout is changed to 40ms not 50ms or 60ms? What's the time we expected from SDM? I hope we don't need to change this again. Thanks Hao > > > > Signed-off-by: Ang Tien Sung <tien.sung.ang@xxxxxxxxx> > > --- > > drivers/fpga/altera-cvp.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c > > index 4ffb9da537d8..5295ff90482b 100644 > > --- a/drivers/fpga/altera-cvp.c > > +++ b/drivers/fpga/altera-cvp.c > > @@ -52,7 +52,7 @@ > > /* V2 Defines */ > > #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */ > > > > -#define V2_CREDIT_TIMEOUT_US 20000 > > +#define V2_CREDIT_TIMEOUT_US 40000 > > #define V2_CHECK_CREDIT_US 10 > > #define V2_POLL_TIMEOUT_US 1000000 > > #define V2_USER_TIMEOUT_US 500000 > > Acked-by: Xu Yilun <yilun.xu@xxxxxxxxx> > > > -- > > 2.25.1
