This patch adds description for UIO support for dfl devices on DFL bus. Signed-off-by: Xu Yilun <yilun.xu@xxxxxxxxx> --- v2: no doc in v1, add it for v2. --- Documentation/fpga/dfl.rst | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 0404fe6..a15e81e 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,29 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +UIO support for DFL devices +=========================== +The FPGA is open for users to be reprogramed with newly developed hardware +components. They could instantiate a new private feature in the DFL, and then +get a DFL device in their system. In some cases users may need a userspace +driver for the DFL device: + +* Users may need to run some diagnostic test for their hardwares. +* Some hardware is designed for specific purposes and does not fit into one of + the standard kernel subsystems. + +This requires the direct access to the MMIO space and interrupt handling in +userspace. We implemented a dfl-uio-pdev module which exposes the UIO device +interfaces. It adds the uio_pdrv_genirq platform device with the resources of +the DFL device, and let the generic UIO platform device driver provide UIO +support to userspace. + +The DFL UIO driver has a special matching algorithem. It will match any DFL +device which could not be handled by other DFL drivers. In this way, it will +not impact the functionality of the features which are already supported by the +system. + + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration -- 2.7.4
