From: Dragos Bogdan <dragos.bogdan@xxxxxxxxxx> This IP core also works and is supported on the Xilinx ZynqMP (UltraScale) FPGA boards. This patch enables the driver to be available on these platforms as well. Signed-off-by: Dragos Bogdan <dragos.bogdan@xxxxxxxxxx> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@xxxxxxxxxx> --- drivers/clk/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4026fac9fac3..44353f257fe2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -239,7 +239,7 @@ config CLK_TWL6040 config COMMON_CLK_AXI_CLKGEN tristate "AXI clkgen driver" - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST + depends on ARCH_ZYNQ || ARCH_ZYNQMP || MICROBLAZE || COMPILE_TEST help Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx FPGAs. It is commonly used in Analog Devices' reference designs. -- 2.25.1
