> -----Original Message-----
> From: linux-fpga-owner@xxxxxxxxxxxxxxx <linux-fpga-owner@xxxxxxxxxxxxxxx>
> On Behalf Of Xu Yilun
> Sent: Thursday, April 16, 2020 11:12 AM
> To: mdf@xxxxxxxxxx; linux-fpga@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx
> Cc: trix@xxxxxxxxxx; bhu@xxxxxxxxxx; Matthew Gerlach
> <matthew.gerlach@xxxxxxxxxxxxxxx>; Xu, Yilun <yilun.xu@xxxxxxxxx>
> Subject: [PATCH 2/2] fpga: dfl: fix bug in port reset handshake
>
> From: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
>
> When putting the port in reset, driver must wait for the soft reset
> acknowledgment bit instead of the soft reset bit.
>
> Fixes: 47c1b19c160f (fpga: dfl: afu: add port ops support)
> Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
> Signed-off-by: Xu Yilun <yilun.xu@xxxxxxxxx>
Thanks for catching this.
Acked-by: Wu Hao <hao.wu@xxxxxxxxx>
> ---
> drivers/fpga/dfl-afu-main.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
> index b0c3178..3fa2c59 100644
> --- a/drivers/fpga/dfl-afu-main.c
> +++ b/drivers/fpga/dfl-afu-main.c
> @@ -83,7 +83,8 @@ int __afu_port_disable(struct platform_device *pdev)
> * on this port and minimum soft reset pulse width has elapsed.
> * Driver polls port_soft_reset_ack to determine if reset done by HW.
> */
> - if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v &
> PORT_CTRL_SFTRST,
> + if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
> + v & PORT_CTRL_SFTRST_ACK,
> RST_POLL_INVL, RST_POLL_TIMEOUT)) {
> dev_err(&pdev->dev, "timeout, fail to reset device\n");
> return -ETIMEDOUT;
> --
> 2.7.4
