On 2013-04-10 12:28, Archit Taneja wrote: > Ah ok, I remember it now. One of the DPLL's divider's output is DSS_FCK. > We get the parent's rate and iterate through all the possible hsdivider > values to get the closest pixel clock. We don't/can't change > dpll4_m4_clk as such, we just need to know it's rate for our calculations. > > So yes, we need dpll4_m4_clk, we just need to rename it to a better > thing. Like dss_clk_parent. Right. And the field name in struct dss_features, "clk_name" is rather vague. At some point we should fix the omap clk framework so that we can set the dss fck directly. Presuming there's no good reason to have it as it is now. I'll apply the patch as it is now. Tomi
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