On Tue, 2012-09-25 at 11:49 +0530, Archit Taneja wrote: > Extend the DISPC fifo functions to also configure the writeback FIFO thresholds. > > The most optimal configuration for writeback is to push out data to the > interconnect the moment writeback pushes enough pixels in the FIFO to form a > burst. This reduces the chance of writeback overflowing it's FIFO. Hmm, why is this optimal? The FIFO for WB is the output fifo, right? In mem-to-mem mode the whole WB pipeline can stall, so the fifo can't overflow? If so, isn't it better to collect more data and flush all that to the memory, instead of sending each burst-size piece one by one? Then again, if the input side is reading pixels from the memory all the time, even if the output fifo helps to keep the output side idle for longer periods, it probably doesn't help as the input side keeps the memory bus awake. Tomi
Attachment:
signature.asc
Description: This is a digitally signed message part
