> Hi,
>
> I am working on DT binding for Tegra DVFS.
>
> For Tegra, DVFS node mainly consists of frequency and voltage pairs.
> Frequency in the pair may change for different process. E.g. for process
> 1 CPU clock frequency could be 900MHz at 1V while for process 2 it could
> be 1GHz at 1V.
> Tegra uses vendor specific ids to identify the correct frequency table.
Hello,
It seems that in the example, the values in "voltage-array" and
"frequencies" are switched.
Anyway, what about SoCs that reads information from IEM (or any other module)
to measure gate delays or some other value to set the appriorate voltage values
for every possible frequency? I remember some of Exynos SoCs have been doing
it; dynamically measure the characteristics at boot-up time and apply voltages
accordingly; they couldn't identify it based on the chip-id or simply by reading
a single register.
Cheers!
MyungJoo.
>
> Following is the proposed binding for voltage and frequency tables used
> in DVFS. Looking for comments/suggestions to make it generic.
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