On Wed, 2011-01-05 at 11:07 -0800, David Miller wrote:
> > Those are 32 bit addresses, so I suppose I should be getting the
> base
> > address for the registers accesses from region 1, right?
>
> Actually, I take back what I said earlier. Region 1 is a Memory
> region not an I/O region.
>
> It looks like you'll have to find a way to get at the implicit
> I/O space for the PCI domain this framebuffer is behind and
> construct the implicit VGA addresses by hand.
>
> There is a way to do this, via pcibios_bus_to_resource(). You could
> do something like:
>
> struct s3fb_info {
> ...
> void __iomem *vga_iobase;
> ...
> static int __devinit s3_pci_probe(struct pci_dev *dev, const struct
> pci_device_id *id)
> {
> struct pci_bus_region bus_reg;
> struct resource vga_res;
> ...
> bus_reg.start = 0;
> bus_reg.end = 64 * 1024;
>
> vga_res.flags = IORESOURCE_IO;
>
> pcibios_bus_to_resource(dev, &bus_reg, &vga_res);
>
> par->vga_iobase = (void __iomem *) vga_res.start;
>
> Then replace all NULL vga_*() initial arguments in the driver
> with par->vga_iobase.
No wonder it was crashing, there was nothing to access with region 1! I
will do as you suggest, and see if it works. Thank you!
--
Tactical Nuclear Kittens
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