the clock gate for MIPI-DSI controller is placed at CLK_GATE_IP1[2]
so it adds a clock object to clock framework for MIPI-DSI clock gating.
Signed-off-by: Inki Dae <inki.dae@xxxxxxxxxxx>
Signed-off-by: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
---
arch/arm/mach-s5pv210/clock.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index dab6ef3..a8d5235 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -365,6 +365,12 @@ static struct clk init_clocks_disable[] = {
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<0),
}, {
+ .name = "dsim",
+ .id = -1,
+ .parent = &clk_hclk_dsys.clk,
+ .enable = s5pv210_clk_ip1_ctrl,
+ .ctrlbit = (1<<2),
+ }, {
.name = "cfcon",
.id = 0,
.parent = &clk_hclk_psys.clk,
--
1.7.0.4
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