Russell King - ARM Linux wrote: > On Thu, May 13, 2010 at 08:47:11AM +1000, Benjamin Herrenschmidt wrote: > > Now, in the case at hand, which is my ARM based NAS, I believe this > > is non cache-coherent and thus uses cache flush ops. I don't know ARM > > well enough but I would expect these to be implicit barriers. Russell ? > > Nico ? > > ARMv5 doesn't have a weak memory ordering model, and doesn't have any > memory barrier instructions. It does have buffered writes, doesn't it? Are they always flushed by the cache flush ops? -- Jamie -- To unsubscribe from this list: send the line "unsubscribe linux-ext4" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
