Re: AMP on an SMP system

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Il 02/08/2013 14:13, Michael Schnell ha scritto:
On 08/02/2013 01:42 PM, Robert Schwebel wrote:
Before hacking around (which might also lead to interesting solutions),
I would start using a kernel with preempt-rt support and play with the
cpu affinity:

http://lxr.linux.no/#linux+v3.10.4/Documentation/kernel-parameters.txt#L1257



Robert !
Nice to see you here (I do own your "Embedded Linux Handbuch für
Entwickler" :-) )

Thanks for the pointer !

I do already know "preempt-rt", but I was not aware of cpu affinity.

So this might help.

In fact I need a way to do very guaranteed low latency. regarding the
high clock rate (about 1 GHz) modern ARM chips can provide, maybe
preempt-rt with the cpu affinity might be a decent way to go.


Just to be clear: at the moment there isn't an easy way to dedicate "completely" a cpu for a task. The last time I tried (some years ago actually) to use exclusive cpu set, the scheduler didn't do a good work because it was designed for SMP, not SMP minus some piece. However you can try and you can report your results. It would be interesting.

The raining questions include
  - how to calculate the maximum latency that can be guaranteed ? (i.e.
does the Kernel impose any spinlocks and interrupt disables on the would
be AMP subsystem ?)

No. You can use full dyn tick for example to disable timer interrupt, but it has got some pros and cons, especially with very low latency requirement.

  - how to assign an interrupt (e.g. a dedicated timer) to the subsystem ?

Interrupt handler are kernel thread, so you can schedule your kernel thread on your "normal" cpu.

  - Do the interrupts immediately call the ISR of the cpu "under
affinity" or is some additional latency imposed by the Kernel

AFAIC, no latency for cpu "under affinity".

(and how
many cpu cycles at max are needed to enter the ISR) ?

It's difficult to answer to this question because the performance depends on your system. From my last statistics I saw that with an rt linux kernel you can stay below 50us for the interrupt latency.

Marco
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