Bitops optimization with specialized instructions is common practice in popular ISAs, this patch set uses RISC-V Zbb extension to optimize four bitops: __ffs, __fls, ffs and fls. The first patch rearranges the content in hwcap.h and cpufeature.h, it helps to avoid a cyclic header including issue for patch 2. The second patch leverages the alternative mechanism to dynamically apply this optimization. Thanks, Xiao v4: - Simplify the asm code in ffs() and fls() by moving general logic into C implementation. (Charlie) - Add a comment to decorating the large #ifdef block. (Charlie) - Link to v3: https://lore.kernel.org/all/20230926094655.3102758-1-xiao.w.wang@xxxxxxxxx/ v3: - Fix riscv32 build issue reported by kernel test robot. V3 changes "hwcap.h" to "cpufeature.h" for files where cpu feature detection APIs are used. (Yujie) - Link to v2: https://lore.kernel.org/all/20230920074653.2509631-1-xiao.w.wang@xxxxxxxxx/ v2: - Remove the "EFI_" prefix from macro name "EFI_NO_ALTERNATIVE" to make it generic. (Ard) - patch-1 is added, it's based on "RISC-V: Enable cbo.zero in usermode". (Andrew) - Link to v1: https://lore.kernel.org/all/20230806024715.3061589-1-xiao.w.wang@xxxxxxxxx/ Xiao Wang (2): riscv: Rearrange hwcap.h and cpufeature.h riscv: Optimize bitops with Zbb extension arch/riscv/include/asm/bitops.h | 255 +++++++++++++++++++++++++- arch/riscv/include/asm/cpufeature.h | 83 +++++++++ arch/riscv/include/asm/elf.h | 2 +- arch/riscv/include/asm/hwcap.h | 91 --------- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 2 +- arch/riscv/kvm/aia.c | 2 +- arch/riscv/kvm/main.c | 2 +- arch/riscv/kvm/tlb.c | 2 +- arch/riscv/kvm/vcpu_fp.c | 2 +- arch/riscv/kvm/vcpu_onereg.c | 2 +- arch/riscv/kvm/vcpu_vector.c | 2 +- drivers/bitopstest/Kconfig | 1 + drivers/clocksource/timer-riscv.c | 2 +- drivers/firmware/efi/libstub/Makefile | 2 +- drivers/perf/riscv_pmu_sbi.c | 2 +- 17 files changed, 349 insertions(+), 106 deletions(-) -- 2.25.1
