On Fri, Jul 28, 2023 at 11:09:04AM +0200, Ard Biesheuvel wrote:
> Update the trampoline code so its arguments are passed via RDI and RSI,
> which matches the ordinary SysV calling convention for x86_64. This will
> allow this code to be called directly from C.
>
> Acked-by: Kirill A. Shutemov <kirill.shutemov@xxxxxxxxxxxxxxx>
> Signed-off-by: Ard Biesheuvel <ardb@xxxxxxxxxx>
> ---
> arch/x86/boot/compressed/head_64.S | 26 +++++++++-----------
> arch/x86/boot/compressed/pgtable.h | 2 +-
> 2 files changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
> index 1892679be2b6897a..491d985be75fd5b0 100644
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -443,9 +443,9 @@ SYM_CODE_START(startup_64)
> movq %r15, %rdi /* pass struct boot_params pointer */
> call paging_prepare
>
> - /* Save the trampoline address in RCX */
> - movq %rax, %rcx
> -
> + /* Pass the trampoline address and boolean flag as args #1 and #2 */
> + movq %rax, %rdi
> + movq %rdx, %rsi
> leaq TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax
> call *%rax
>
> @@ -534,15 +534,15 @@ SYM_FUNC_END(.Lrelocated)
> /*
> * This is the 32-bit trampoline that will be copied over to low memory.
> *
> - * ECX contains the base address of the trampoline memory.
> - * Non zero RDX means trampoline needs to enable 5-level paging.
> + * EDI contains the base address of the trampoline memory.
> + * Non-zero ESI means trampoline needs to enable 5-level paging.
> */
This is confusing - this talks about 32-bit and 32-bit registers but
uses the 64-bit calling convention because it gets called by 64-bit
code. Please add a short sentence clarifying that.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
