Dan Williams wrote:
> While going to create include/linux/cxl.h for some cross-subsystem CXL
> definitions I noticed that include/linux/cxl_err.h was already present.
> That header has no reason to be global, and it duplicates the RAS
> Capability Structure definitions in drivers/cxl/cxl.h.
Change looks fine to me but I'm failing to find these duplicate
definitions? Without any duplication it seems like stronger change to me.
> A follow-on patch
> can consider unifying the CXL native error tracing with the CPER error
> printing.
>
> Also fixed up the spec reference as the latest released spec is v3.0.
>
> Cc: Smita Koralahalli <Smita.KoralahalliChannabasappa@xxxxxxx>
Reviewed-by: Ira Weiny <ira.weiny@xxxxxxxxx>
> Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx>
> ---
> drivers/firmware/efi/cper_cxl.c | 12 +++++++++++-
> include/linux/cxl_err.h | 22 ----------------------
> 2 files changed, 11 insertions(+), 23 deletions(-)
> delete mode 100644 include/linux/cxl_err.h
>
> diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c
> index 53e435c4f310..a55771b99a97 100644
> --- a/drivers/firmware/efi/cper_cxl.c
> +++ b/drivers/firmware/efi/cper_cxl.c
> @@ -9,7 +9,6 @@
>
> #include <linux/cper.h>
> #include "cper_cxl.h"
> -#include <linux/cxl_err.h>
>
> #define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0)
> #define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1)
> @@ -19,6 +18,17 @@
> #define PROT_ERR_VALID_DVSEC BIT_ULL(5)
> #define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6)
>
> +/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */
> +struct cxl_ras_capability_regs {
> + u32 uncor_status;
> + u32 uncor_mask;
> + u32 uncor_severity;
> + u32 cor_status;
> + u32 cor_mask;
> + u32 cap_control;
> + u32 header_log[16];
> +};
> +
> static const char * const prot_err_agent_type_strs[] = {
> "Restricted CXL Device",
> "Restricted CXL Host Downstream Port",
> diff --git a/include/linux/cxl_err.h b/include/linux/cxl_err.h
> deleted file mode 100644
> index 629e1bdeda44..000000000000
> --- a/include/linux/cxl_err.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (C) 2022 Advanced Micro Devices, Inc.
> - *
> - * Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@xxxxxxx>
> - */
> -
> -#ifndef LINUX_CXL_ERR_H
> -#define LINUX_CXL_ERR_H
> -
> -/* CXL RAS Capability Structure, CXL v3.1 sec 8.2.4.16 */
> -struct cxl_ras_capability_regs {
> - u32 uncor_status;
> - u32 uncor_mask;
> - u32 uncor_severity;
> - u32 cor_status;
> - u32 cor_mask;
> - u32 cap_control;
> - u32 header_log[16];
> -};
> -
> -#endif //__CXL_ERR_
>
