The purpose of this series is to remove any explicit cache maintenance for coherency during early boot. Software managed coherency is error prone and tedious, and running with the MMU off is generally bad for performance, and it becomes unnecessary if we simply retain the cacheable 1:1 mapping of all of system RAM provided by EFI, and use it to populate the initial ID map page tables. After setting up this preliminary ID map, we disable the MMU, drop to EL1, reprogram the MAIR, TCR and SCTLR registers as before, and proceed as usual, avoiding the need for any manipulations of memory while the MMU and caches are off. The only properties of the firmware provided 1:1 map we rely on is that it does not require any explicit cache maintenance for coherency, and that it covers the entire memory footprint of the image, including the BSS and padding at the end - all else is under control of the kernel itself, as before. The final patch updates the EFI stub code so that it no longer disables the MMU and caches or cleans the entire image to the PoC. Note that some cache maintenace for I/D coherence may still be needed, in the zboot case (which decompresses and boots a compressed kernel image) or in cases where the image is moved in memory. Changes since v6: - drop the 64k alignment patch, which is not strictly a prerequisite, and will be revisited later if needed - add back EFI stub changes now that all dependencies are in mainline - panic() the kernel later in the boot if we detected a non-EFI boot occurring with the MMU and caches enabled Changes since v5: - add a special entry point into the boot sequence that is to be used by EFI only, and only permit booting with the MMU enabled when using that boot path; - omit the final patch that would need to go via the EFI tree in any case - adding the new entrypoint specific for EFI makes it conflict even more badly, and I'll try to revisit this during the merge window or simply defer the final piece for the next release; Changes since v4: - add patch to align the callers of finalise_el2() - also clean HYP text to the PoC when booting at EL2 with the MMU on - add a warning and a taint when doing non-EFI boot with the MMU and caches enabled - rebase onto zboot changes in efi/next - this means that patches #6 and #7 will not apply onto arm64/for-next so a shared stable branch will be needed if we want to queue this up for v6.2 Changes since v3: - drop EFI_LOADER_CODE memory type patch that has been queued in the mean time - rebased onto [partial] series that moves efi-entry.S into the libstub/ source directory - fixed a correctness issue in patch #2 Cc: Will Deacon <will@xxxxxxxxxx> Cc: Catalin Marinas <catalin.marinas@xxxxxxx> Cc: Marc Zyngier <maz@xxxxxxxxxx> Cc: Mark Rutland <mark.rutland@xxxxxxx> Ard Biesheuvel (6): arm64: head: Move all finalise_el2 calls to after __enable_mmu arm64: kernel: move identity map out of .text mapping arm64: head: record the MMU state at primary entry arm64: head: avoid cache invalidation when entering with the MMU on arm64: head: Clean the ID map and the HYP text to the PoC if needed efi: arm64: enter with MMU and caches enabled arch/arm64/include/asm/efi.h | 2 + arch/arm64/kernel/head.S | 89 +++++++++++++++----- arch/arm64/kernel/image-vars.h | 5 +- arch/arm64/kernel/setup.c | 17 +++- arch/arm64/kernel/sleep.S | 6 +- arch/arm64/kernel/vmlinux.lds.S | 2 +- arch/arm64/mm/cache.S | 1 + arch/arm64/mm/proc.S | 2 - drivers/firmware/efi/libstub/Makefile | 4 +- drivers/firmware/efi/libstub/arm64-entry.S | 67 --------------- drivers/firmware/efi/libstub/arm64-stub.c | 26 ++++-- drivers/firmware/efi/libstub/arm64.c | 41 +++++++-- 12 files changed, 151 insertions(+), 111 deletions(-) delete mode 100644 drivers/firmware/efi/libstub/arm64-entry.S -- 2.39.0
