On Mon, Oct 17, 2022 at 07:16:40PM +0200, Ard Biesheuvel wrote:
> diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S
> index 61a87fa1c305..1c1be004a271 100644
> --- a/arch/arm64/kernel/efi-entry.S
> +++ b/arch/arm64/kernel/efi-entry.S
> @@ -23,15 +23,6 @@ SYM_CODE_START(efi_enter_kernel)
> add x19, x0, x2 // relocated Image entrypoint
> mov x20, x1 // DTB address
>
> - /*
> - * Clean the copied Image to the PoC, and ensure it is not shadowed by
> - * stale icache entries from before relocation.
> - */
> - ldr w1, =kernel_size
> - add x1, x0, x1
> - bl dcache_clean_poc
> - ic ialluis
> -
> /*
> * Clean the remainder of this routine to the PoC
> * so that we can safely disable the MMU and caches.
[...]
> diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c
> index 598c76c4bbaa..e767a5ac8c3d 100644
> --- a/drivers/firmware/efi/libstub/arm64-stub.c
> +++ b/drivers/firmware/efi/libstub/arm64-stub.c
[...]
> @@ -174,5 +174,13 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
> *image_addr = *reserve_addr;
> memcpy((void *)*image_addr, _text, kernel_size);
>
> +clean_image_to_poc:
> + /*
> + * Clean the copied Image to the PoC, and ensure it is not shadowed by
> + * stale icache entries from before relocation.
> + */
> + dcache_clean_poc(*image_addr, *image_addr + kernel_size);
> + asm("ic ialluis");
Does this need some barriers, at least a DSB? The original code had DSB
and ISB, though not immediately after the IC instruction.
--
Catalin
