On Fri, Sep 17, 2021 at 5:57 AM Huacai Chen <chenhuacai@xxxxxxxxxxx> wrote:
> This patch adds basic boot, setup and reset routines for LoongArch.
> LoongArch uses UEFI-based firmware and uses ACPI as the boot protocol.
This needs to be reviewed by the maintainers for the EFI and ACPI subsystems,
I added them to Cc here. If you add lines like
Cc: Ard Biesheuvel <ardb@xxxxxxxxxx>
Cc: linux-efi@xxxxxxxxxxxxxxx
in the patch description before your Signed-off-by, then git-send-email will
Cc them automatically without you having to spam them with the entire series.
In particular, I know that Ard previously complained that you did not use the
EFI boot protocol correctly, and I want to make sure that he's happy with the
final version.
> +static ssize_t boardinfo_show(struct kobject *kobj,
> + struct kobj_attribute *attr, char *buf)
> +{
> + return sprintf(buf,
> + "BIOS Information\n"
> + "Vendor\t\t\t: %s\n"
> + "Version\t\t\t: %s\n"
> + "ROM Size\t\t: %d KB\n"
> + "Release Date\t\t: %s\n\n"
> + "Board Information\n"
> + "Manufacturer\t\t: %s\n"
> + "Board Name\t\t: %s\n"
> + "Family\t\t\t: LOONGSON64\n\n",
> + b_info.bios_vendor, b_info.bios_version,
> + b_info.bios_size, b_info.bios_release_date,
> + b_info.board_vendor, b_info.board_name);
> +}
> +
> +static struct kobj_attribute boardinfo_attr = __ATTR(boardinfo, 0444,
> + boardinfo_show, NULL);
> +
> +static int __init boardinfo_init(void)
> +{
> + if (!efi_kobj)
> + return -EINVAL;
> +
> + return sysfs_create_file(efi_kobj, &boardinfo_attr.attr);
> +}
> +late_initcall(boardinfo_init);
I see you have documented this interface for your mips machines,
but nothing else uses it.
I think some of this information should be part of the soc_device,
either in addition to, or in place of this sysfs file.
Isn't there an existing method to do this on x86/arm/ia64 machines?
> +static int constant_set_state_periodic(struct clock_event_device *evt)
> +{
> + unsigned long period;
> + unsigned long timer_config;
> +
> + raw_spin_lock(&state_lock);
> +
> + period = const_clock_freq / HZ;
> + timer_config = period & CSR_TCFG_VAL;
> + timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN);
> + csr_writeq(timer_config, LOONGARCH_CSR_TCFG);
> +
> + raw_spin_unlock(&state_lock);
I see this pattern in a couple of places, using a spinlock or raw_spinlock
to guard MMIO access, but on many architectures a register write is
not serialized by the following spin_unlock, unless you insert another
read from the same address in there. E.g. on PCIe, writes are always
posted and it would not work.
Can you confirm that it works correctly on CSR registers in loongarch?
Arnd
