Decode aarch64 additions and substractions and create stack_ops for
instructions interacting with SP or FP.
Signed-off-by: Julien Thierry <jthierry@xxxxxxxxxx>
---
tools/objtool/arch/arm64/decode.c | 84 +++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 8ae822f553ca..0f312dd1b146 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -23,6 +23,13 @@
#include "../../../arch/arm64/lib/aarch64-insn.c"
+static unsigned long sign_extend(unsigned long x, int nbits)
+{
+ unsigned long sign_bit = (x >> (nbits - 1)) & 1;
+
+ return ((~0UL + (sign_bit ^ 1)) << nbits) | x;
+}
+
bool arch_callee_saved_reg(unsigned char reg)
{
switch (reg) {
@@ -98,6 +105,53 @@ int arch_decode_hint_reg(struct instruction *insn, u8 sp_reg)
return -1;
}
+static struct stack_op *arm_make_add_op(enum aarch64_insn_register dest,
+ enum aarch64_insn_register src,
+ int val)
+{
+ struct stack_op *op;
+
+ op = calloc(1, sizeof(*op));
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = dest;
+ op->src.reg = src;
+ op->src.type = val != 0 ? OP_SRC_ADD : OP_SRC_REG;
+ op->src.offset = val;
+
+ return op;
+}
+
+static void arm_decode_add_sub_imm(u32 instr, bool set_flags,
+ enum insn_type *type,
+ unsigned long *immediate,
+ struct list_head *ops_list)
+{
+ u32 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, instr);
+ u32 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, instr);
+
+ *type = INSN_OTHER;
+ *immediate = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, instr);
+
+ if (instr & AARCH64_INSN_LSL_12)
+ *immediate <<= 12;
+
+ if ((!set_flags && rd == AARCH64_INSN_REG_SP) ||
+ rd == AARCH64_INSN_REG_FP ||
+ rn == AARCH64_INSN_REG_FP ||
+ rn == AARCH64_INSN_REG_SP) {
+ struct stack_op *op;
+ int value;
+
+ if (aarch64_insn_is_subs_imm(instr) || aarch64_insn_is_sub_imm(instr))
+ value = -*immediate;
+ else
+ value = *immediate;
+
+ op = arm_make_add_op(rd, rn, value);
+ list_add_tail(&op->list, ops_list);
+ }
+}
+
int arch_decode_instruction(const struct elf *elf, const struct section *sec,
unsigned long offset, unsigned int maxlen,
unsigned int *len, enum insn_type *type,
@@ -121,6 +175,36 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
case AARCH64_INSN_CLS_UNKNOWN:
WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
return -1;
+ case AARCH64_INSN_CLS_DP_IMM:
+ /* Mov register to and from SP are aliases of add_imm */
+ if (aarch64_insn_is_add_imm(insn) ||
+ aarch64_insn_is_sub_imm(insn))
+ arm_decode_add_sub_imm(insn, false, type, immediate,
+ ops_list);
+ else if (aarch64_insn_is_adds_imm(insn) ||
+ aarch64_insn_is_subs_imm(insn))
+ arm_decode_add_sub_imm(insn, true, type, immediate,
+ ops_list);
+ else
+ *type = INSN_OTHER;
+ break;
+ case AARCH64_INSN_CLS_DP_REG:
+ if (aarch64_insn_is_mov_reg(insn)) {
+ enum aarch64_insn_register rd;
+ enum aarch64_insn_register rm;
+
+ rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn);
+ rm = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn);
+ if (rd == AARCH64_INSN_REG_FP || rm == AARCH64_INSN_REG_FP) {
+ struct stack_op *op;
+
+ op = arm_make_add_op(rd, rm, 0);
+ list_add_tail(&op->list, ops_list);
+ break;
+ }
+ }
+ *type = INSN_OTHER;
+ break;
default:
*type = INSN_OTHER;
break;
--
2.25.4
