On Mon, Sep 21, 2020 at 5:41 PM Ard Biesheuvel <ardb@xxxxxxxxxx> wrote: > Update the p2v patching code so we can deal with displacements that are > not a multiple of 16 MiB but of 2 MiB, to prevent wasting of up to 14 MiB > of physical RAM when running on a platform where the start of memory is > not correctly aligned. > > For the ARM code path, this simply comes down to using two add/sub > instructions instead of one for the carryless version, and patching > each of them with the correct immediate depending on the rotation > field. For the LPAE calculation, it patches the MOVW instruction with > up to 12 bits of offset. > > For the Thumb2 code path, patching more than 11 bits off displacement > is somewhat cumbersome, and given that 11 bits produce a minimum > alignment of 2 MiB, which is also the granularity for LPAE block > mappings, it makes sense to stick to 2 MiB for the new p2v requirement. > > Suggested-by: Zhen Lei <thunder.leizhen@xxxxxxxxxx> > Signed-off-by: Ard Biesheuvel <ardb@xxxxxxxxxx> My understanding of what is going on is limited to the high level of things, and being able to do this is just a great thing so FWIW: Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx> If you or Russell need more thorough review I can sit down and try to understand at the bit granularity what is going on but it requires a bunch of time. Just tell me if you need this. Yours, Linus Walleij
