Hi, On 3/4/20 7:26 PM, Ard Biesheuvel wrote:
On Wed, 4 Mar 2020 at 11:39, Hans de Goede <hdegoede@xxxxxxxxxx> wrote:Hi, On 2/6/20 3:35 PM, Ard Biesheuvel wrote:On Thu, 6 Feb 2020 at 14:31, Hans de Goede <hdegoede@xxxxxxxxxx> wrote:Hi, On 12/18/19 6:01 PM, Ard Biesheuvel wrote:From: Matthew Garrett <matthewgarrett@xxxxxxxxxx> Add an option to disable the busmaster bit in the control register on all PCI bridges during the invocation of ExitBootServices() and passing control to the runtime kernel. System firmware may configure the IOMMU to prevent malicious PCI devices from being able to attack the OS via DMA. However, since firmware can't guarantee that the OS is IOMMU-aware, it will tear down IOMMU configuration when ExitBootServices() is called. This leaves a window between where a hostile device could still cause damage before Linux configures the IOMMU again. If CONFIG_EFI_DISABLE_PCI_DMA is enabled or the "efi=disable_pci_dma" command line argument is passed, the EFI stub will clear the busmaster bit on all PCI bridges before ExitBootServices() completes. This will prevent any malicious PCI devices from being able to perform DMA until the kernel reenables busmastering after configuring the IOMMU. This option is disabled when in EFI mixed mode environments (ie, 64-bit kernels with a 32-bit EFI implementation), given that the use of EFI events is not supported in this case. This option may cause failures with some poorly behaved hardware and should not be enabled without testing. The kernel commandline options "efi=disable_pci_dma" or "efi=no_disable_pci_dma" may be used to override the default. Co-developed-by: Matthew Garrett <mjg59@xxxxxxxxxx> Signed-off-by: Matthew Garrett <mjg59@xxxxxxxxxx> [ardb: use EFI events to defer DMA disabling to the end of ExitBootServices()] Signed-off-by: Ard Biesheuvel <ardb@xxxxxxxxxx>I guess this might not be the latest version of this patch, but this does seem to be the thread where most discussion on it has happened. My personal kernel tree atm consists of v5.5 + efi/next + my own patches and yesterday I noticed that will not boot on a Lenovo X1 7th gen connected to a Lenovo thunderbolt 3 gen 2 dock. My first hunch was that I have CONFIG_EFI_DISABLE_PCI_DMA=y and that that was causing it and indeed that is the problem. So as (somewhat) expected CONFIG_EFI_DISABLE_PCI_DMA=y indeed stops the kernel from booting on some systems. When I hit this problem the efistub prints 2 messages and then the system just hangs: exit_boot() failed! efi_main() failed! When I boot the system without it being connected to the thunderbolt dock then efi=disable_pci_dma works fine. Let me know if I can do anything to help and getting booting while connected to the dock to work with efi=disable_pci_dma.Thanks Hans. Can you run the UEFI shell on this system? If so, could you share the output of devtree, both in the docked and the undocked states? That should help us pinpoint which device is throwing an error at ExitBootServices() time due to its driver having been disconnected.Sorry for being slow to respond. Attached are the outputs of devtree in both states. Not sure if the list will accept this, but you should get a direct copy.Interesting. The only difference that UEFI seems to know about in terms of device hierarchy is a XHCI controller with a Realtek USB NIC attached. Could you try unloading the driver for that manually, or disconnecting it? Or disconnect the whole thing from the shell?
How would I go about that / do that ?
If just unloading the realtek driver does not make a difference, but unload/disconnecting the xhci makes it work, it is likely that it this feature will break a lot of systems.
Notice that it is not just the XHCI controller which gets added though, there also is an extra PCI-e switch added to the route to the XHCI controller, I've attached both docked and undocked lspci output under Linux. I guess this might be transparent from a UEFI pov though. Regards, Hans
--- Downloads/devtree-not-docked 2020-03-04 19:18:14.596315280 +0100
+++ Downloads/devtree-docked 2020-03-04 19:18:08.856257969 +0100
@@ -11,6 +11,7 @@
Ctrl[] PciRoot(0x0)/Pci(0x0,0x0)
Ctrl[] Intel(R) Graphics Controller
Ctrl[] EDP1
+ Ctrl[] DP1
Ctrl[] Primary Console Output Device
Ctrl[] PciRoot(0x0)/Pci(0x4,0x0)
Ctrl[] PciRoot(0x0)/Pci(0x8,0x0)
@@ -44,6 +45,110 @@
Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x0,0x0)
Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x0,0x0)/Pci(0x0,0x0)
Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)
+ Ctrl[] eXtensible Host Controller (USB 3.0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x3,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x4,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x3,0x0)/USB(0x0,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x0,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x2,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x3,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x3,0x0)/USB(0x0,0x0)/USB(0x1,0x0)
+ Ctrl[] Realtek USB Ethernet Controller
<lots of network stuff>
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x0,0x0)/USB(0x3,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x0,0x0)/USB(0x3,0x1)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x0,0x0)/USB(0x3,0x2)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x0,0x0)/USB(0x3,0x3)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x2,0x0)/USB(0x3,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x3,0x0)/USB(0x0,0x0)
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x2,0x0)/Pci(0x0,0x0)/USB(0x1,0x0)/USB(0x0,0x0)/USB(0x3,0x0)/USB(0x1,0x0)
+ Ctrl[] Generic Usb Keyboard
+ Ctrl[] Primary Console Input Device
+ Ctrl[] Generic Usb Mouse
+ Ctrl[] Primary Console Input Device
+ Ctrl[] Generic Usb Mouse
+ Ctrl[] Primary Console Input Device
+ Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x1,0x0)/Pci(0x0,0x0)/Pci(0x4,0x0)
Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x2,0x0)
Ctrl[] eXtensible Host Controller (USB 3.0)
Ctrl[] PciRoot(0x0)/Pci(0x1D,0x4)/Pci(0x0,0x0)/Pci(0x4,0x0)
@@ -69,5 +174,3 @@
Ctrl[] VenHw(2C0EEABD-4107-44A8-A787-2E38FFC52B2B)
Ctrl[] VenHw(48B9FB42-B3B9-4A0E-BF66-36AE1C302369)
Ctrl[] VenHw(A7F26116-CFDC-4296-8224-ED7D140170C7)
- Ctrl[] MemoryMapped(0xB,0xFF2E0000,0xFF37FFFF)
- Ctrl[] Fv(B92CF322-8AFA-4AA4-B946-005DF1D69778)
00:00.0 Host bridge: Intel Corporation Coffee Lake HOST and DRAM Controller (rev 0c) 00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (Whiskey Lake) (rev 02) 00:04.0 Signal processing controller: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Thermal Subsystem (rev 0c) 00:08.0 System peripheral: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model 00:12.0 Signal processing controller: Intel Corporation Cannon Point-LP Thermal Controller (rev 11) 00:14.0 USB controller: Intel Corporation Cannon Point-LP USB 3.1 xHCI Controller (rev 11) 00:14.2 RAM memory: Intel Corporation Cannon Point-LP Shared SRAM (rev 11) 00:14.3 Network controller: Intel Corporation Cannon Point-LP CNVi [Wireless-AC] (rev 11) 00:15.0 Serial bus controller [0c80]: Intel Corporation Cannon Point-LP Serial IO I2C Controller #0 (rev 11) 00:15.1 Serial bus controller [0c80]: Intel Corporation Cannon Point-LP Serial IO I2C Controller #1 (rev 11) 00:16.0 Communication controller: Intel Corporation Cannon Point-LP MEI Controller #1 (rev 11) 00:16.3 Serial controller: Intel Corporation Cannon Point-LP Keyboard and Text (KT) Redirection (rev 11) 00:1d.0 PCI bridge: Intel Corporation Cannon Point-LP PCI Express Root Port #9 (rev f1) 00:1d.4 PCI bridge: Intel Corporation Cannon Point-LP PCI Express Root Port #13 (rev f1) 00:1f.0 ISA bridge: Intel Corporation Cannon Point-LP LPC Controller (rev 11) 00:1f.3 Audio device: Intel Corporation Cannon Point-LP High Definition Audio Controller (rev 11) 00:1f.4 SMBus: Intel Corporation Cannon Point-LP SMBus Controller (rev 11) 00:1f.5 Serial bus controller [0c80]: Intel Corporation Cannon Point-LP SPI Controller (rev 11) 00:1f.6 Ethernet controller: Intel Corporation Ethernet Connection (6) I219-LM (rev 11) 03:00.0 Non-Volatile memory controller: Sandisk Corp WD Black 2018/PC SN720 NVMe SSD 05:00.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:00.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:01.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:02.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:04.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 07:00.0 System peripheral: Intel Corporation JHL6540 Thunderbolt 3 NHI (C step) [Alpine Ridge 4C 2016] (rev 02) 08:00.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge DD 2018] (rev 06) 09:02.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge DD 2018] (rev 06) 09:04.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge DD 2018] (rev 06) 0a:00.0 USB controller: Intel Corporation JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018] (rev 06) 2d:00.0 USB controller: Intel Corporation JHL6540 Thunderbolt 3 USB Controller (C step) [Alpine Ridge 4C 2016] (rev 02)
00:00.0 Host bridge: Intel Corporation Coffee Lake HOST and DRAM Controller (rev 0c) 00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (Whiskey Lake) (rev 02) 00:04.0 Signal processing controller: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Thermal Subsystem (rev 0c) 00:08.0 System peripheral: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model 00:12.0 Signal processing controller: Intel Corporation Cannon Point-LP Thermal Controller (rev 11) 00:14.0 USB controller: Intel Corporation Cannon Point-LP USB 3.1 xHCI Controller (rev 11) 00:14.2 RAM memory: Intel Corporation Cannon Point-LP Shared SRAM (rev 11) 00:14.3 Network controller: Intel Corporation Cannon Point-LP CNVi [Wireless-AC] (rev 11) 00:15.0 Serial bus controller [0c80]: Intel Corporation Cannon Point-LP Serial IO I2C Controller #0 (rev 11) 00:15.1 Serial bus controller [0c80]: Intel Corporation Cannon Point-LP Serial IO I2C Controller #1 (rev 11) 00:16.0 Communication controller: Intel Corporation Cannon Point-LP MEI Controller #1 (rev 11) 00:16.3 Serial controller: Intel Corporation Cannon Point-LP Keyboard and Text (KT) Redirection (rev 11) 00:1d.0 PCI bridge: Intel Corporation Cannon Point-LP PCI Express Root Port #9 (rev f1) 00:1d.4 PCI bridge: Intel Corporation Cannon Point-LP PCI Express Root Port #13 (rev f1) 00:1f.0 ISA bridge: Intel Corporation Cannon Point-LP LPC Controller (rev 11) 00:1f.3 Audio device: Intel Corporation Cannon Point-LP High Definition Audio Controller (rev 11) 00:1f.4 SMBus: Intel Corporation Cannon Point-LP SMBus Controller (rev 11) 00:1f.5 Serial bus controller [0c80]: Intel Corporation Cannon Point-LP SPI Controller (rev 11) 00:1f.6 Ethernet controller: Intel Corporation Ethernet Connection (6) I219-LM (rev 11) 03:00.0 Non-Volatile memory controller: Sandisk Corp WD Black 2018/PC SN720 NVMe SSD 05:00.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:00.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:01.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:02.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 06:04.0 PCI bridge: Intel Corporation JHL6540 Thunderbolt 3 Bridge (C step) [Alpine Ridge 4C 2016] (rev 02) 07:00.0 System peripheral: Intel Corporation JHL6540 Thunderbolt 3 NHI (C step) [Alpine Ridge 4C 2016] (rev 02) 2d:00.0 USB controller: Intel Corporation JHL6540 Thunderbolt 3 USB Controller (C step) [Alpine Ridge 4C 2016] (rev 02)
-[0000:00]-+-00.0
+-02.0
+-04.0
+-08.0
+-12.0
+-14.0
+-14.2
+-14.3
+-15.0
+-15.1
+-16.0
+-16.3
+-1d.0-[03]----00.0
+-1d.4-[05-52]----00.0-[06-52]--+-00.0-[07]----00.0
| +-01.0-[08-2c]----00.0-[09-2c]--+-02.0-[0a]----00.0
| | \-04.0-[0b-2c]--
| +-02.0-[2d]----00.0
| \-04.0-[2e-52]--
+-1f.0
+-1f.3
+-1f.4
+-1f.5
\-1f.6
-[0000:00]-+-00.0
+-02.0
+-04.0
+-08.0
+-12.0
+-14.0
+-14.2
+-14.3
+-15.0
+-15.1
+-16.0
+-16.3
+-1d.0-[03]----00.0
+-1d.4-[05-52]----00.0-[06-52]--+-00.0-[07]----00.0
| +-01.0-[08-2c]--
| +-02.0-[2d]----00.0
| \-04.0-[2e-52]--
+-1f.0
+-1f.3
+-1f.4
+-1f.5
\-1f.6
