In preparation for turning the decompressor's cache clean/flush operations into proper by-VA maintenance for v7 cores, pass the start and end addresses of the regions that need cache maintenance into cache_clean_flush in registers r0 and r1. Currently, all implementations of cache_clean_flush ignore these values, so no functional change is expected as a result of this patch. Signed-off-by: Ard Biesheuvel <ardb@xxxxxxxxxx> --- arch/arm/boot/compressed/head.S | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 674e55400cfd..12d631503bfa 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -533,12 +533,19 @@ dtb_check_done: add sp, sp, r6 #endif + adr r0, restart + ldr r1, .Lclean_size + add r0, r0, r6 + add r1, r1, r0 bl cache_clean_flush badr r0, restart add r0, r0, r6 mov pc, r0 + .align 2 +.Lclean_size: .long _edata - restart + wont_overwrite: /* * If delta is zero, we are running at the address we were linked at. @@ -629,6 +636,11 @@ not_relocated: mov r0, #0 add r2, sp, #0x10000 @ 64k max mov r3, r7 bl decompress_kernel + + get_inflated_image_size r1, r2, r3 + + mov r0, r4 @ start of inflated image + add r1, r1, r0 @ end of inflated image bl cache_clean_flush bl cache_off @@ -1182,6 +1194,9 @@ __armv7_mmu_cache_off: /* * Clean and flush the cache to maintain consistency. * + * On entry, + * r0 = start address + * r1 = end address (exclusive) * On exit, * r1, r2, r3, r9, r10, r11, r12 corrupted * This routine must preserve: -- 2.17.1
