Re: [PATCH] efi/arm: enable CP15 DMB instructions before cleaning the cache

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On Mon, 8 Apr 2019 at 11:20, Vladimir Murzin <vladimir.murzin@xxxxxxx> wrote:
>
> On 4/7/19 7:19 PM, Ard Biesheuvel wrote:
> > Actually, the CP15 ISB is not usable here, and using the v7 ISB breaks
> > v6. Would reading back SCTLR suffice?
>
>
> I think instr_sync macro should do the trick.
>

This code should run on v7 when compiled for v6, and instr_sync uses
the CP15 ISB in that case, which we cannot use since that is what we
are enabling in the first place.

I'll go with Marc's suggestion, which should work in all cases
(although it may require a .arch directive to ensure the isb is
accepted)



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