On Mon, Nov 16, 2015 at 07:32:36PM +0100, Ard Biesheuvel wrote:
> +static inline void efi_set_pgd(struct mm_struct *mm)
> +{
> + if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
> + __check_vmalloc_seq(mm);
> +
> + cpu_switch_mm(mm->pgd, mm);
> +
> + flush_tlb_all();
> + if (icache_is_vivt_asid_tagged())
> + __flush_icache_all();
> +}
I don't think that's sufficient. There's a gap between switching the mm
and flushing the TLBs where we could have different global TLB entries
from those in the page tables - and that can cause problems with CPUs
which speculatively prefetch. Some CPUs raise exceptions for this...
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according to speedtest.net.
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