The following patch convert over to setting the XCLK register usage with the new em28xx_write_reg() function. Please let me know if you have any questions. Thanks, Devin -- Devin J. Heitmueller http://www.devinheitmueller.com AIM: devinheitmueller
em28xx: cleanup XCLK register usage From: Devin Heitmueller <devin.heitmueller@xxxxxxxxx> Convert over to setting the XCLK register usage with the new em28xx_write_reg() function. Thanks to Ray Lu from Empia for providing the em2860/2880 datasheet. Signed-off-by: Devin Heitmueller <devin.heitmueller@xxxxxxxxx> Index: v4l-dvb/linux/drivers/media/video/em28xx/em28xx-cards.c =================================================================== --- v4l-dvb.orig/linux/drivers/media/video/em28xx/em28xx-cards.c 2008-11-24 18:57:57.000000000 -0500 +++ v4l-dvb/linux/drivers/media/video/em28xx/em28xx-cards.c 2008-11-24 19:37:38.000000000 -0500 @@ -1401,7 +1401,9 @@ case EM2882_BOARD_PINNACLE_HYBRID_PRO: case EM2883_BOARD_KWORLD_HYBRID_A316: case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1415,7 +1417,9 @@ break; case EM2882_BOARD_TERRATEC_HYBRID_XS: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1437,7 +1441,9 @@ case EM2880_BOARD_KWORLD_DVB_310U: case EM2870_BOARD_KWORLD_350U: case EM2881_BOARD_DNT_DA2_HYBRID: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1456,7 +1462,9 @@ case EM2880_BOARD_MSI_DIGIVOX_AD: case EM2880_BOARD_MSI_DIGIVOX_AD_II: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1471,11 +1479,14 @@ case EM2750_BOARD_UNKNOWN: case EM2750_BOARD_DLCW_130: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x0a", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_FREQUENCY_48MHZ); break; case EM2861_BOARD_PLEXTOR_PX_TV100U: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1486,7 +1497,9 @@ case EM2861_BOARD_KWORLD_PVRTV_300U: case EM2880_BOARD_KWORLD_DVB_305U: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1498,7 +1511,9 @@ break; case EM2870_BOARD_KWORLD_355U: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1509,7 +1524,9 @@ break; case EM2870_BOARD_COMPRO_VIDEOMATE: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1530,7 +1547,9 @@ break; case EM2870_BOARD_TERRATEC_XS_MT2060: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1558,12 +1577,17 @@ em28xx_write_regs(dev, 0x08, "\xfe", 1); mdelay(70); /* switch em2880 rc protocol */ - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x22", 1); + /* djh - I have serious doubts this is right... */ + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_10MHZ); /* should be added ir_codes here */ break; case EM2820_BOARD_GADMEI_UTV310: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1572,8 +1596,9 @@ break; case EM2860_BOARD_GADMEI_UTV330: - /* Turn on IR */ - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x07", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); @@ -1581,7 +1606,9 @@ break; case EM2820_BOARD_MSI_VOX_USB_2: - em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); + em28xx_write_reg(dev, EM28XX_R0F_XCLK, + EM28XX_XCLK_IR_RC5_MODE | + EM28XX_XCLK_FREQUENCY_12MHZ); em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ); Index: v4l-dvb/linux/drivers/media/video/em28xx/em28xx-reg.h =================================================================== --- v4l-dvb.orig/linux/drivers/media/video/em28xx/em28xx-reg.h 2008-11-24 18:57:54.000000000 -0500 +++ v4l-dvb/linux/drivers/media/video/em28xx/em28xx-reg.h 2008-11-24 19:11:50.000000000 -0500 @@ -51,6 +51,24 @@ #define EM28XX_R0E_AUDIOSRC 0x0e #define EM28XX_R0F_XCLK 0x0f +/* em28xx XCLK Register (0x0f) */ +#define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */ +#define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */ +#define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */ +#define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10 +#define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */ +#define EM28XX_XCLK_FREQUENCY_15MHZ 0x01 +#define EM28XX_XCLK_FREQUENCY_10MHZ 0x02 +#define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03 +#define EM28XX_XCLK_FREQUENCY_6MHZ 0x04 +#define EM28XX_XCLK_FREQUENCY_5MHZ 0x05 +#define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06 +#define EM28XX_XCLK_FREQUENCY_12MHZ 0x07 +#define EM28XX_XCLK_FREQUENCY_20MHZ 0x08 +#define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09 +#define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a +#define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b + #define EM28XX_R10_VINMODE 0x10 #define EM28XX_R11_VINCTRL 0x11 #define EM28XX_R12_VINENABLE 0x12 /* */
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