Hello all.
In my last messages I wrote that problem that inside
dvb_ca_en50221_write_data it clear flag SW because of writing new value
where this flag not present.
/* OK, set HC bit */
if ((status = ca->pub->write_cam_control(ca->pub, slot,
CTRLIF_COMMAND,
IRQEN | CMDREG_HC)) != 0)
goto exit;
So some producer of CAM modules follow very clearly to standard of en50221
cam module initialization part and ignore this because of in write
operation SW bit not sent. I make changes in this operation and hold SW
bit and after this all modules (I have many of them) start to work.
So read carefully standard and analyze code in Linux driver and you will
understand. About delays. It do not present in standard after FR is
present you can immediately begin write operation module is ready to
receive data. Try my patch that I already sent in this list, it do all
like I describe all like in standard.
--
Bendyak Evgen
Simon Baxter wrote:
I've seen these problems too. Mark Anderson sent me the following patch,
which introduces delays as you mention.
This fixed my CAM access problems I had with dvb_ca_en50221.c
--
Bendyak Evgen
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