laasa schrieb: > Second try: Here again with patchfile and shifted from budget to > budget-ci (thanks to marco for some hints). > > Sources > - Manus snapshot at http://jusst.de/manu/stb0899-v4l-dvb.tar.bz > - the szap-sources from http://dev.kewl.org/tmp/hvr4000/szap2.tgz > > Envoirenment: > - TT3200 (SAA7146AH, STB0899 C2L, STB6100, LNBP21 PD, 27000 MHz, board > B2S3000 Rev 1.0 TT2006.1) > - Tested with Linux-Kernel 2.6.16-45 (from kernel.org) and > 2.6.17-chw-8 (MythTV R5D1): must be <= 2.6.17 > > Procedure for compiling and loading of drivers: > - unpack kernel-sources (to /usr/src/linux) if necessary > - unpack v4l-dvb-sources (to /usr/src/v4l-dvb) > - unpack szap2-sources (to /usr/src/szap) > - change to /usr/src/szap > - make > - make install => check if szap2 now is installed > - change to /usr/src/v4l-dvb > - patch the tree > - v4l-scripts-make_myconfig.pl > - rename .version in /usr/src/v4l-dvb/v4l > - make > - unload all dvb-driver (e.g. make rmmod) > - make install > - modprobe budget-ci > - szap -r ... > - xine ... > > Notes: > - the TT3200 is build into modules budget-ci > - to tune a channel you must (most times) tune to different channels > (for me ZDF and Kika are good candidates to get a LOCK) > > Problems: > - everytime with the locking of PLL (sometimes after some trys on > different DVB-S-channels, on some DVB-S-channels and all DVB-S2-channels > never) > - It seems to be a problem with higher frequences (higest successfuly > tuned frequency is 11836 MHz, e.g. ARD => ProSieben ... not work) > > > ------------------------------------------------------------------------ > > diff -urNp v4l-dvb.org/linux/drivers/media/dvb/dvb-core/dvb_frontend.c v4l-dvb/linux/drivers/media/dvb/dvb-core/dvb_frontend.c > --- v4l-dvb.org/linux/drivers/media/dvb/dvb-core/dvb_frontend.c 2007-02-24 11:57:13.000000000 +0100 > +++ v4l-dvb/linux/drivers/media/dvb/dvb-core/dvb_frontend.c 2007-05-06 20:03:50.000000000 +0200 > @@ -1563,6 +1563,11 @@ static int dvb_frontend_ioctl(struct ino > memset(&fetunesettings, 0, sizeof(struct dvb_frontend_tune_settings)); > memcpy(&fetunesettings.parameters, parg, sizeof (struct dvb_frontend_parameters)); > > + olddrv_to_newapi(fe,&fepriv->fe_params, &fepriv->parameters, FE_QPSK); > + > + /* Request the search algorithm to search */ > + fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; > + > /* force auto frequency inversion if requested */ > if (dvb_force_auto_inversion) { > fepriv->parameters.inversion = INVERSION_AUTO; > @@ -1893,13 +1898,15 @@ void dvb_frontend_detach(struct dvb_fron > { > void *ptr; > > - if (fe->ops.release_sec) { > + ptr = (void*)fe->ops.release_sec; > + if (ptr) { > fe->ops.release_sec(fe); > - symbol_put_addr(fe->ops.release_sec); > + symbol_put_addr(ptr); > } > - if (fe->ops.tuner_ops.release) { > + ptr = (void*)fe->ops.tuner_ops.release; > + if (ptr) { > fe->ops.tuner_ops.release(fe); > - symbol_put_addr(fe->ops.tuner_ops.release); > + symbol_put_addr(ptr); > } > ptr = (void*)fe->ops.release; > if (ptr) { > diff -urNp v4l-dvb.org/linux/drivers/media/dvb/dvb-core/dvb_frontend.h v4l-dvb/linux/drivers/media/dvb/dvb-core/dvb_frontend.h > --- v4l-dvb.org/linux/drivers/media/dvb/dvb-core/dvb_frontend.h 2007-02-24 11:57:15.000000000 +0100 > +++ v4l-dvb/linux/drivers/media/dvb/dvb-core/dvb_frontend.h 2007-05-06 19:33:25.000000000 +0200 > @@ -199,6 +199,8 @@ struct dvb_tuner_ops { > > int (*get_frequency)(struct dvb_frontend *fe, u32 *frequency); > int (*get_bandwidth)(struct dvb_frontend *fe, u32 *bandwidth); > + int (*set_frequency)(struct dvb_frontend *fe, u32 frequency); > + int (*set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth); > > #define TUNER_STATUS_LOCKED 1 > int (*get_status)(struct dvb_frontend *fe, u32 *status); > diff -urNp v4l-dvb.org/linux/drivers/media/dvb/frontends/stb0899_drv.c v4l-dvb/linux/drivers/media/dvb/frontends/stb0899_drv.c > --- v4l-dvb.org/linux/drivers/media/dvb/frontends/stb0899_drv.c 2007-02-19 00:26:05.000000000 +0100 > +++ v4l-dvb/linux/drivers/media/dvb/frontends/stb0899_drv.c 2007-05-06 20:08:35.000000000 +0200 > @@ -31,7 +31,8 @@ > #include "stb0899_priv.h" > #include "stb0899_reg.h" > > -static unsigned int verbose = 5; > +//static unsigned int verbose = 5; > +static unsigned int verbose = 0; > module_param(verbose, int, 0644); > > /* C/N in dB/10, NIRM/NIRL */ > @@ -2013,6 +2014,7 @@ struct dvb_frontend *stb0899_attach(stru > state->i2c = i2c; > state->frontend.ops = stb0899_ops; > state->frontend.demodulator_priv = state; > + state->delsys = DVBFE_DELSYS_DVBS; > > stb0899_wakeup(&state->frontend); > if (stb0899_get_dev_id(state) == -ENODEV) { > diff -urNp v4l-dvb.org/linux/drivers/media/dvb/frontends/stb6100.c v4l-dvb/linux/drivers/media/dvb/frontends/stb6100.c > --- v4l-dvb.org/linux/drivers/media/dvb/frontends/stb6100.c 2007-02-10 17:37:22.000000000 +0100 > +++ v4l-dvb/linux/drivers/media/dvb/frontends/stb6100.c 2007-05-06 20:08:40.000000000 +0200 > @@ -27,7 +27,8 @@ > #include "dvb_frontend.h" > #include "stb6100.h" > > -static unsigned int verbose; > +//static unsigned int verbose; > +static unsigned int verbose = 0; > module_param(verbose, int, 0644); > > > @@ -423,6 +424,20 @@ static int stb6100_set_frequency(struct > if ((rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO])) < 0) > return rc; > > +///XXX > + { > + int rc; > + unsigned long start = jiffies; > + > + while ((rc = stb6100_read_reg(state, STB6100_LD)) >=0) { > + if (rc & STB6100_LD_LOCK) > + break; > + if (jiffies - start > 100) > + break; > + msleep(10); > + } > + } > + > msleep(5); /* wait for LO to lock */ > regs[STB6100_VCO] &= ~STB6100_VCO_OSCH; /* vco search disabled */ > regs[STB6100_VCO] |= STB6100_VCO_OCK; /* search clock off */ > @@ -525,6 +540,8 @@ static struct dvb_tuner_ops stb6100_ops > .set_state = stb6100_set_state, > .get_frequency = stb6100_get_frequency, > .get_bandwidth = stb6100_get_bandwidth, > + .set_frequency = stb6100_set_frequency, > + .set_bandwidth = stb6100_set_bandwidth, > .release = stb6100_release > }; > > diff -urNp v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget-ci.c v4l-dvb/linux/drivers/media/dvb/ttpci/budget-ci.c > --- v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget-ci.c 2007-02-22 14:20:08.000000000 +0100 > +++ v4l-dvb/linux/drivers/media/dvb/ttpci/budget-ci.c 2007-05-06 19:31:18.000000000 +0200 > @@ -47,6 +47,10 @@ > #include "bsbe1.h" > #include "bsru6.h" > > +#include "stb0899_drv.h" > +#include "stb0899_reg.h" > +#include "stb6100.h" > + > /* > * Regarding DEBIADDR_IR: > * Some CI modules hang if random addresses are read. > @@ -1086,6 +1090,528 @@ static struct stv0297_config dvbc_philip > > > > +/* TT S2-3200 DVB-S (STB0899) Inittab */ > +static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = { > + > +// 0x0000000b , /* SYSREG */ > + { STB0899_DEV_ID , 0x81 }, > + { STB0899_DISCNTRL1 , 0x32 }, > + { STB0899_DISCNTRL2 , 0x80 }, > + { STB0899_DISRX_ST0 , 0x04 }, > + { STB0899_DISRX_ST1 , 0x00 }, > + { STB0899_DISPARITY , 0x00 }, > + { STB0899_DISFIFO , 0x00 }, > + { STB0899_DISSTATUS , 0x20 }, > + { STB0899_DISF22 , 0x8c }, > + { STB0899_DISF22RX , 0x9a }, > + //SYSREG ? > + { STB0899_ACRPRESC , 0x11 }, > + { STB0899_ACRDIV1 , 0x0a }, > + { STB0899_ACRDIV2 , 0x05 }, > + { STB0899_DACR1 , 0x00 }, > + { STB0899_DACR2 , 0x00 }, > + { STB0899_OUTCFG , 0x00 }, > + { STB0899_MODECFG , 0x00 }, > + { STB0899_IRQSTATUS_3 , 0x30 }, > + { STB0899_IRQSTATUS_2 , 0x00 }, > + { STB0899_IRQSTATUS_1 , 0x00 }, > + { STB0899_IRQSTATUS_0 , 0x00 }, > + { STB0899_IRQMSK_3 , 0xf3 }, > + { STB0899_IRQMSK_2 , 0xfc }, > + { STB0899_IRQMSK_1 , 0xff }, > + { STB0899_IRQMSK_0 , 0xff }, > + { STB0899_IRQCFG , 0x00 }, > + { STB0899_I2CCFG , 0x88 }, > + { STB0899_I2CRPT , 0x5c }, > + { STB0899_IOPVALUE5 , 0x00 }, > + { STB0899_IOPVALUE4 , 0x20 }, > + { STB0899_IOPVALUE3 , 0xc9 }, > + { STB0899_IOPVALUE2 , 0x90 }, > + { STB0899_IOPVALUE1 , 0x40 }, > + { STB0899_IOPVALUE0 , 0x00 }, > + { STB0899_GPIO00CFG , 0x82 }, > + { STB0899_GPIO01CFG , 0x82 }, > + { STB0899_GPIO02CFG , 0x82 }, > + { STB0899_GPIO03CFG , 0x82 }, > + { STB0899_GPIO04CFG , 0x82 }, > + { STB0899_GPIO05CFG , 0x82 }, > + { STB0899_GPIO06CFG , 0x82 }, > + { STB0899_GPIO07CFG , 0x82 }, > + { STB0899_GPIO08CFG , 0x82 }, > + { STB0899_GPIO09CFG , 0x82 }, > + { STB0899_GPIO10CFG , 0x82 }, > + { STB0899_GPIO11CFG , 0x82 }, > + { STB0899_GPIO12CFG , 0x82 }, > + { STB0899_GPIO13CFG , 0x82 }, > + { STB0899_GPIO14CFG , 0x82 }, > + { STB0899_GPIO15CFG , 0x82 }, > + { STB0899_GPIO16CFG , 0x82 }, > + { STB0899_GPIO17CFG , 0x82 }, > + { STB0899_GPIO18CFG , 0x82 }, > + { STB0899_GPIO19CFG , 0x82 }, > + { STB0899_GPIO20CFG , 0x82 }, > + { STB0899_SDATCFG , 0xb8 }, > + { STB0899_SCLTCFG , 0xba }, > + { STB0899_AGCRFCFG , 0x1c }, // 0x11 > + { STB0899_GPIO22 , 0x82 }, // AGCBB2CFG > + { STB0899_GPIO21 , 0x91 }, // AGCBB1CFG > + { STB0899_DIRCLKCFG , 0x82 }, > + { STB0899_CLKOUT27CFG , 0x7e }, > + { STB0899_STDBYCFG , 0x82 }, > + { STB0899_CS0CFG , 0x82 }, > + { STB0899_CS1CFG , 0x82 }, > + { STB0899_DISEQCOCFG , 0x20 }, > + { STB0899_GPIO32CFG , 0x82 }, > + { STB0899_GPIO33CFG , 0x82 }, > + { STB0899_GPIO34CFG , 0x82 }, > + { STB0899_GPIO35CFG , 0x82 }, > + { STB0899_GPIO36CFG , 0x82 }, > + { STB0899_GPIO37CFG , 0x82 }, > + { STB0899_GPIO38CFG , 0x82 }, > + { STB0899_GPIO39CFG , 0x82 }, > + { STB0899_NCOARSE , 0x15 }, // 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz > + { STB0899_SYNTCTRL , 0x02 }, // 0x00 = CLK from CLKI, 0x02 = CLK from XTALI > + { STB0899_FILTCTRL , 0x00 }, > + { STB0899_SYSCTRL , 0x00 }, > + { STB0899_STOPCLK1 , 0x20 }, > + { STB0899_STOPCLK2 , 0x00 }, > + { STB0899_INTBUFSTATUS , 0x00 }, > + { STB0899_INTBUFCTRL , 0x0a }, > + { 0xffff , 0xff }, > +}; > + > +static const struct stb0899_s2_reg tt3200_stb0899_s2_init_2[] = { > + > + { STB0899_OFF0_DMD_STATUS , STB0899_BASE_DMD_STATUS , 0x00000103 }, /* DMDSTATUS */ > + { STB0899_OFF0_CRL_FREQ , STB0899_BASE_CRL_FREQ , 0x3ed1da56 }, /* CRLFREQ */ > + { STB0899_OFF0_BTR_FREQ , STB0899_BASE_BTR_FREQ , 0x00004000 }, /* BTRFREQ */ > + { STB0899_OFF0_IF_AGC_GAIN , STB0899_BASE_IF_AGC_GAIN , 0x00002ade }, /* IFAGCGAIN */ > + { STB0899_OFF0_BB_AGC_GAIN , STB0899_BASE_BB_AGC_GAIN , 0x000001bc }, /* BBAGCGAIN */ > + { STB0899_OFF0_DC_OFFSET , STB0899_BASE_DC_OFFSET , 0x00000200 }, /* DCOFFSET */ > + { STB0899_OFF0_DMD_CNTRL , STB0899_BASE_DMD_CNTRL , 0x0000000f }, /* DMDCNTRL */ > + > + { STB0899_OFF0_IF_AGC_CNTRL , STB0899_BASE_IF_AGC_CNTRL , 0x03fb4a20 }, /* IFAGCCNTRL */ > + { STB0899_OFF0_BB_AGC_CNTRL , STB0899_BASE_BB_AGC_CNTRL , 0x00200c97 }, /* BBAGCCNTRL */ > + > + { STB0899_OFF0_CRL_CNTRL , STB0899_BASE_CRL_CNTRL , 0x00000016 }, /* CRLCNTRL */ > + { STB0899_OFF0_CRL_PHS_INIT , STB0899_BASE_CRL_PHS_INIT , 0x00000000 }, /* CRLPHSINIT */ > + { STB0899_OFF0_CRL_FREQ_INIT , STB0899_BASE_CRL_FREQ_INIT , 0x00000000 }, /* CRLFREQINIT */ > + { STB0899_OFF0_CRL_LOOP_GAIN , STB0899_BASE_CRL_LOOP_GAIN , 0x00000000 }, /* CRLLOOPGAIN */ > + { STB0899_OFF0_CRL_NOM_FREQ , STB0899_BASE_CRL_NOM_FREQ , 0x3ed097b6 }, /* CRLNOMFREQ */ > + { STB0899_OFF0_CRL_SWP_RATE , STB0899_BASE_CRL_SWP_RATE , 0x00000000 }, /* CRLSWPRATE */ > + { STB0899_OFF0_CRL_MAX_SWP , STB0899_BASE_CRL_MAX_SWP , 0x00000000 }, /* CRLMAXSWP */ > + { STB0899_OFF0_CRL_LK_CNTRL , STB0899_BASE_CRL_LK_CNTRL , 0x0f6cdc01 }, /* CRLLKCNTRL */ > + { STB0899_OFF0_DECIM_CNTRL , STB0899_BASE_DECIM_CNTRL , 0x00000000 }, /* DECIMCNTRL */ > + { STB0899_OFF0_BTR_CNTRL , STB0899_BASE_BTR_CNTRL , 0x00003993 }, /* BTRCNTRL */ > + { STB0899_OFF0_BTR_LOOP_GAIN , STB0899_BASE_BTR_LOOP_GAIN , 0x000d3c6f }, /* BTRLOOPGAIN */ > + { STB0899_OFF0_BTR_PHS_INIT , STB0899_BASE_BTR_PHS_INIT , 0x00000000 }, /* BTRPHSINIT */ > + { STB0899_OFF0_BTR_FREQ_INIT , STB0899_BASE_BTR_FREQ_INIT , 0x00000000 }, /* BTRFREQINIT */ > + { STB0899_OFF0_BTR_NOM_FREQ , STB0899_BASE_BTR_NOM_FREQ , 0x0238e38e }, /* BTRNOMFREQ */ > + { STB0899_OFF0_BTR_LK_CNTRL , STB0899_BASE_BTR_LK_CNTRL , 0x00000000 }, /* BTRLKCNTRL */ > + { STB0899_OFF0_DECN_CNTRL , STB0899_BASE_DECN_CNTRL , 0x00000000 }, /* DECNCNTRL */ > + { STB0899_OFF0_TP_CNTRL , STB0899_BASE_TP_CNTRL , 0x00000000 }, /* TPCNTRL */ > + { STB0899_OFF0_TP_BUF_STATUS , STB0899_BASE_TP_BUF_STATUS , 0x00000000 }, /* TPBUFSTATUS */ > + { STB0899_OFF0_DC_ESTIM , STB0899_BASE_DC_ESTIM , 0x00000000 }, /* DCESTIM */ > + { STB0899_OFF0_FLL_CNTRL , STB0899_BASE_FLL_CNTRL , 0x00000000 }, /* FLLCNTRL */ > + { STB0899_OFF0_FLL_FREQ_WD , STB0899_BASE_FLL_FREQ_WD , 0x40070000 }, /* FLLFREQWD */ > + { STB0899_OFF0_ANTI_ALIAS_SEL , STB0899_BASE_ANTI_ALIAS_SEL , 0x00000001 }, /* ANTIALIASSEL */ > + { STB0899_OFF0_RRC_ALPHA , STB0899_BASE_RRC_ALPHA , 0x00000002 }, /* RRCALPHA */ > + { STB0899_OFF0_DC_ADAPT_LSHFT , STB0899_BASE_DC_ADAPT_LSHFT , 0x00000000 }, /* DCADAPTISHFT */ > + { STB0899_OFF0_IMB_OFFSET , STB0899_BASE_IMB_OFFSET , 0x0000fe01 }, /* IMBOFFSET */ > + { STB0899_OFF0_IMB_ESTIMATE , STB0899_BASE_IMB_ESTIMATE , 0x00000000 }, /* IMBESTIMATE */ > + { STB0899_OFF0_IMB_CNTRL , STB0899_BASE_IMB_CNTRL , 0x00000001 }, /* IMBCNTRL */ > + { STB0899_OFF0_IF_AGC_CNTRL2 , STB0899_BASE_IF_AGC_CNTRL2 , 0x00005007 }, /* IFAGCCNTRL2 */ > + { STB0899_OFF0_DMD_CNTRL2 , STB0899_BASE_DMD_CNTRL2 , 0x00000002 }, /* DMDCNTRL2 */ > + { STB0899_OFF0_TP_BUFFER , STB0899_BASE_TP_BUFFER , 0x00000000 }, /* TPBUFFER */ > + { STB0899_OFF0_TP_BUFFER1 , STB0899_BASE_TP_BUFFER1 , 0x00000000 }, /* TPBUFFER1 */ > + { STB0899_OFF0_TP_BUFFER2 , STB0899_BASE_TP_BUFFER2 , 0x00000000 }, /* TPBUFFER2 */ > + { STB0899_OFF0_TP_BUFFER3 , STB0899_BASE_TP_BUFFER3 , 0x00000000 }, /* TPBUFFER3 */ > + { STB0899_OFF0_TP_BUFFER4 , STB0899_BASE_TP_BUFFER4 , 0x00000000 }, /* TPBUFFER4 */ > + { STB0899_OFF0_TP_BUFFER5 , STB0899_BASE_TP_BUFFER5 , 0x00000000 }, /* TPBUFFER5 */ > + { STB0899_OFF0_TP_BUFFER6 , STB0899_BASE_TP_BUFFER6 , 0x00000000 }, /* TPBUFFER6 */ > + { STB0899_OFF0_TP_BUFFER7 , STB0899_BASE_TP_BUFFER7 , 0x00000000 }, /* TPBUFFER7 */ > + { STB0899_OFF0_TP_BUFFER8 , STB0899_BASE_TP_BUFFER8 , 0x00000000 }, /* TPBUFFER8 */ > + { STB0899_OFF0_TP_BUFFER9 , STB0899_BASE_TP_BUFFER9 , 0x00000000 }, /* TPBUFFER9 */ > + { STB0899_OFF0_TP_BUFFER10 , STB0899_BASE_TP_BUFFER10 , 0x00000000 }, /* TPBUFFER10 */ > + { STB0899_OFF0_TP_BUFFER11 , STB0899_BASE_TP_BUFFER11 , 0x00000000 }, /* TPBUFFER11 */ > + { STB0899_OFF0_TP_BUFFER12 , STB0899_BASE_TP_BUFFER12 , 0x00000000 }, /* TPBUFFER12 */ > + { STB0899_OFF0_TP_BUFFER13 , STB0899_BASE_TP_BUFFER13 , 0x00000000 }, /* TPBUFFER13 */ > + { STB0899_OFF0_TP_BUFFER14 , STB0899_BASE_TP_BUFFER14 , 0x00000000 }, /* TPBUFFER14 */ > + { STB0899_OFF0_TP_BUFFER15 , STB0899_BASE_TP_BUFFER15 , 0x00000000 }, /* TPBUFFER15 */ > + { STB0899_OFF0_TP_BUFFER16 , STB0899_BASE_TP_BUFFER16 , 0x0000ff00 }, /* TPBUFFER16 */ > + { STB0899_OFF0_TP_BUFFER17 , STB0899_BASE_TP_BUFFER17 , 0x00000100 }, /* TPBUFFER17 */ > + { STB0899_OFF0_TP_BUFFER18 , STB0899_BASE_TP_BUFFER18 , 0x0000fe01 }, /* TPBUFFER18 */ > + { STB0899_OFF0_TP_BUFFER19 , STB0899_BASE_TP_BUFFER19 , 0x000004fe }, /* TPBUFFER19 */ > + { STB0899_OFF0_TP_BUFFER20 , STB0899_BASE_TP_BUFFER20 , 0x0000cfe7 }, /* TPBUFFER20 */ > + { STB0899_OFF0_TP_BUFFER21 , STB0899_BASE_TP_BUFFER21 , 0x0000bec6 }, /* TPBUFFER21 */ > + { STB0899_OFF0_TP_BUFFER22 , STB0899_BASE_TP_BUFFER22 , 0x0000c2bf }, /* TPBUFFER22 */ > + { STB0899_OFF0_TP_BUFFER23 , STB0899_BASE_TP_BUFFER23 , 0x0000c1c1 }, /* TPBUFFER23 */ > + { STB0899_OFF0_TP_BUFFER24 , STB0899_BASE_TP_BUFFER24 , 0x0000c1c1 }, /* TPBUFFER24 */ > + { STB0899_OFF0_TP_BUFFER25 , STB0899_BASE_TP_BUFFER25 , 0x0000c1c1 }, /* TPBUFFER25 */ > + { STB0899_OFF0_TP_BUFFER26 , STB0899_BASE_TP_BUFFER26 , 0x0000c1c1 }, /* TPBUFFER26 */ > + { STB0899_OFF0_TP_BUFFER27 , STB0899_BASE_TP_BUFFER27 , 0x0000c1c0 }, /* TPBUFFER27 */ > + { STB0899_OFF0_TP_BUFFER28 , STB0899_BASE_TP_BUFFER28 , 0x0000c0c0 }, /* TPBUFFER28 */ > + { STB0899_OFF0_TP_BUFFER29 , STB0899_BASE_TP_BUFFER29 , 0x0000c1c1 }, /* TPBUFFER29 */ > + { STB0899_OFF0_TP_BUFFER30 , STB0899_BASE_TP_BUFFER30 , 0x0000c1c1 }, /* TPBUFFER30 */ > + { STB0899_OFF0_TP_BUFFER31 , STB0899_BASE_TP_BUFFER31 , 0x0000c0c1 }, /* TPBUFFER31 */ > + { STB0899_OFF0_TP_BUFFER32 , STB0899_BASE_TP_BUFFER32 , 0x0000c0c1 }, /* TPBUFFER32 */ > + { STB0899_OFF0_TP_BUFFER33 , STB0899_BASE_TP_BUFFER33 , 0x0000c1c1 }, /* TPBUFFER33 */ > + { STB0899_OFF0_TP_BUFFER34 , STB0899_BASE_TP_BUFFER34 , 0x0000c1c1 }, /* TPBUFFER34 */ > + { STB0899_OFF0_TP_BUFFER35 , STB0899_BASE_TP_BUFFER35 , 0x0000c0c1 }, /* TPBUFFER35 */ > + { STB0899_OFF0_TP_BUFFER36 , STB0899_BASE_TP_BUFFER36 , 0x0000c1c1 }, /* TPBUFFER36 */ > + { STB0899_OFF0_TP_BUFFER37 , STB0899_BASE_TP_BUFFER37 , 0x0000c0c1 }, /* TPBUFFER37 */ > + { STB0899_OFF0_TP_BUFFER38 , STB0899_BASE_TP_BUFFER38 , 0x0000c1c1 }, /* TPBUFFER38 */ > + { STB0899_OFF0_TP_BUFFER39 , STB0899_BASE_TP_BUFFER39 , 0x0000c0c0 }, /* TPBUFFER39 */ > + { STB0899_OFF0_TP_BUFFER40 , STB0899_BASE_TP_BUFFER40 , 0x0000c1c0 }, /* TPBUFFER40 */ > + { STB0899_OFF0_TP_BUFFER41 , STB0899_BASE_TP_BUFFER41 , 0x0000c1c1 }, /* TPBUFFER41 */ > + { STB0899_OFF0_TP_BUFFER42 , STB0899_BASE_TP_BUFFER42 , 0x0000c0c0 }, /* TPBUFFER42 */ > + { STB0899_OFF0_TP_BUFFER43 , STB0899_BASE_TP_BUFFER43 , 0x0000c1c0 }, /* TPBUFFER43 */ > + { STB0899_OFF0_TP_BUFFER44 , STB0899_BASE_TP_BUFFER44 , 0x0000c0c1 }, /* TPBUFFER44 */ > + { STB0899_OFF0_TP_BUFFER45 , STB0899_BASE_TP_BUFFER45 , 0x0000c1be }, /* TPBUFFER45 */ > + { STB0899_OFF0_TP_BUFFER46 , STB0899_BASE_TP_BUFFER46 , 0x0000c1c9 }, /* TPBUFFER46 */ > + { STB0899_OFF0_TP_BUFFER47 , STB0899_BASE_TP_BUFFER47 , 0x0000c0da }, /* TPBUFFER47 */ > + { STB0899_OFF0_TP_BUFFER48 , STB0899_BASE_TP_BUFFER48 , 0x0000c0ba }, /* TPBUFFER48 */ > + { STB0899_OFF0_TP_BUFFER49 , STB0899_BASE_TP_BUFFER49 , 0x0000c1c4 }, /* TPBUFFER49 */ > + { STB0899_OFF0_TP_BUFFER50 , STB0899_BASE_TP_BUFFER50 , 0x0000c1bf }, /* TPBUFFER50 */ > + { STB0899_OFF0_TP_BUFFER51 , STB0899_BASE_TP_BUFFER51 , 0x0000c0c1 }, /* TPBUFFER51 */ > + { STB0899_OFF0_TP_BUFFER52 , STB0899_BASE_TP_BUFFER52 , 0x0000c1c0 }, /* TPBUFFER52 */ > + { STB0899_OFF0_TP_BUFFER53 , STB0899_BASE_TP_BUFFER53 , 0x0000c0c1 }, /* TPBUFFER53 */ > + { STB0899_OFF0_TP_BUFFER54 , STB0899_BASE_TP_BUFFER54 , 0x0000c1c1 }, /* TPBUFFER54 */ > + { STB0899_OFF0_TP_BUFFER55 , STB0899_BASE_TP_BUFFER55 , 0x0000c1c1 }, /* TPBUFFER55 */ > + { STB0899_OFF0_TP_BUFFER56 , STB0899_BASE_TP_BUFFER56 , 0x0000c1c1 }, /* TPBUFFER56 */ > + { STB0899_OFF0_TP_BUFFER57 , STB0899_BASE_TP_BUFFER57 , 0x0000c1c1 }, /* TPBUFFER57 */ > + { STB0899_OFF0_TP_BUFFER58 , STB0899_BASE_TP_BUFFER58 , 0x0000c1c1 }, /* TPBUFFER58 */ > + { STB0899_OFF0_TP_BUFFER59 , STB0899_BASE_TP_BUFFER59 , 0x0000c1c1 }, /* TPBUFFER59 */ > + { STB0899_OFF0_TP_BUFFER60 , STB0899_BASE_TP_BUFFER60 , 0x0000c1c1 }, /* TPBUFFER60 */ > + { STB0899_OFF0_TP_BUFFER61 , STB0899_BASE_TP_BUFFER61 , 0x0000c1c1 }, /* TPBUFFER61 */ > + { STB0899_OFF0_TP_BUFFER62 , STB0899_BASE_TP_BUFFER62 , 0x0000c1c1 }, /* TPBUFFER62 */ > + { STB0899_OFF0_TP_BUFFER63 , STB0899_BASE_TP_BUFFER63 , 0x0000c1c0 }, /* TPBUFFER63 */ > + { STB0899_OFF0_RESET_CNTRL , STB0899_BASE_RESET_CNTRL , 0x00000001 }, /* RESETCNTRL */ > + { STB0899_OFF0_ACM_ENABLE , STB0899_BASE_ACM_ENABLE , 0x00005654 }, /* ACMENABLE */ > + { STB0899_OFF0_DESCR_CNTRL , STB0899_BASE_DESCR_CNTRL , 0x00000000 }, /* DESCRCNTRL */ > + { STB0899_OFF0_CSM_CNTRL1 , STB0899_BASE_CSM_CNTRL1 , 0x00020019 }, /* CSMCNTRL1 */ > + { STB0899_OFF0_CSM_CNTRL2 , STB0899_BASE_CSM_CNTRL2 , 0x004b3237 }, /* CSMCNTRL2 */ > + { STB0899_OFF0_CSM_CNTRL3 , STB0899_BASE_CSM_CNTRL3 , 0x0003dd17 }, /* CSMCNTRL3 */ > + { STB0899_OFF0_CSM_CNTRL4 , STB0899_BASE_CSM_CNTRL4 , 0x00008008 }, /* CSMCNTRL4 */ > + { STB0899_OFF0_UWP_CNTRL1 , STB0899_BASE_UWP_CNTRL1 , 0x002a3106 }, /* UWPCNTRL1 */ > + { STB0899_OFF0_UWP_CNTRL2 , STB0899_BASE_UWP_CNTRL2 , 0x0006140a }, /* UWPCNTRL2 */ > + { STB0899_OFF0_UWP_STAT1 , STB0899_BASE_UWP_STAT1 , 0x00008000 }, /* UWPSTAT1 */ > + { STB0899_OFF0_UWP_STAT2 , STB0899_BASE_UWP_STAT2 , 0x00000000 }, /* UWPSTAT2 */ > + { STB0899_OFF0_DMD_STAT2 , STB0899_BASE_DMD_STAT2 , 0x00000000 }, /* DMDSTAT2 */ > + { STB0899_OFF0_FREQ_ADJ_SCALE , STB0899_BASE_FREQ_ADJ_SCALE , 0x00000471 }, /* FREQADJSCALE */ > + { STB0899_OFF0_UWP_CNTRL3 , STB0899_BASE_UWP_CNTRL3 , 0x017b0465 }, /* UWPCNTRL3 */ > + { STB0899_OFF0_SYM_CLK_SEL , STB0899_BASE_SYM_CLK_SEL , 0x00000002 }, /* SYMCLKSEL */ > + { STB0899_OFF0_SOF_SRCH_TO , STB0899_BASE_SOF_SRCH_TO , 0x00196464 }, /* SOFSRCHTO */ > + { STB0899_OFF0_ACQ_CNTRL1 , STB0899_BASE_ACQ_CNTRL1 , 0x00000603 }, /* ACQCNTRL1 */ > + { STB0899_OFF0_ACQ_CNTRL2 , STB0899_BASE_ACQ_CNTRL2 , 0x02046666 }, /* ACQCNTRL2 */ > + { STB0899_OFF0_ACQ_CNTRL3 , STB0899_BASE_ACQ_CNTRL3 , 0x10046583 }, /* ACQCNTRL3 */ > + { STB0899_OFF0_FE_SETTLE , STB0899_BASE_FE_SETTLE , 0x00010404 }, /* FESETTLE */ > + { STB0899_OFF0_AC_DWELL , STB0899_BASE_AC_DWELL , 0x0002aa8a }, /* ACDWELL */ > + { STB0899_OFF0_ACQUIRE_TRIG , STB0899_BASE_ACQUIRE_TRIG , 0x00000000 }, /* ACQUIRETRIG */ > + { STB0899_OFF0_LOCK_LOST , STB0899_BASE_LOCK_LOST , 0x00000001 }, /* LOCKLOST */ > + { STB0899_OFF0_ACQ_STAT1 , STB0899_BASE_ACQ_STAT1 , 0x00000500 }, /* ACQSTAT1 */ > + { STB0899_OFF0_ACQ_TIMEOUT , STB0899_BASE_ACQ_TIMEOUT , 0x0028a0a0 }, /* ACQTIMEOUT */ > + { STB0899_OFF0_ACQ_TIME , STB0899_BASE_ACQ_TIME , 0x00000000 }, /* ACQTIME */ > + { STB0899_OFF0_FINAL_AGC_CNTRL , STB0899_BASE_FINAL_AGC_CNTRL , 0x00800c17 }, /* FINALAGCCNTRL*/ > + { STB0899_OFF0_FINAL_AGC_GAIN , STB0899_BASE_FINAL_AGC_GAIN , 0x00000000 }, /* FINALAGCCGAIN*/ > + { STB0899_OFF0_EQUALIZER_INIT , STB0899_BASE_EQUALIZER_INIT , 0x00000000 }, /* EQUILIZERINIT*/ > + { STB0899_OFF0_EQ_CNTRL , STB0899_BASE_EQ_CNTRL , 0x00054802 }, /* EQCNTL */ > + { STB0899_OFF0_EQ_I_INIT_COEFF_0, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF0 */ > + { STB0899_OFF1_EQ_I_INIT_COEFF_1, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF1 */ > + { STB0899_OFF2_EQ_I_INIT_COEFF_2, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF2 */ > + { STB0899_OFF3_EQ_I_INIT_COEFF_3, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF3 */ > + { STB0899_OFF4_EQ_I_INIT_COEFF_4, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF4 */ > + { STB0899_OFF5_EQ_I_INIT_COEFF_5, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000400 }, /* EQIINITCOEFF5 */ > + { STB0899_OFF6_EQ_I_INIT_COEFF_6, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF6 */ > + { STB0899_OFF7_EQ_I_INIT_COEFF_7, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF7 */ > + { STB0899_OFF8_EQ_I_INIT_COEFF_8, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF8 */ > + { STB0899_OFF9_EQ_I_INIT_COEFF_9, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF9 */ > + { STB0899_OFFa_EQ_I_INIT_COEFF_10,STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF10*/ > + { STB0899_OFF0_EQ_Q_INIT_COEFF_0, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF0 */ > + { STB0899_OFF1_EQ_Q_INIT_COEFF_1, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF1 */ > + { STB0899_OFF2_EQ_Q_INIT_COEFF_2, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF2 */ > + { STB0899_OFF3_EQ_Q_INIT_COEFF_3, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF3 */ > + { STB0899_OFF4_EQ_Q_INIT_COEFF_4, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF4 */ > + { STB0899_OFF5_EQ_Q_INIT_COEFF_5, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF5 */ > + { STB0899_OFF6_EQ_Q_INIT_COEFF_6, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF6 */ > + { STB0899_OFF7_EQ_Q_INIT_COEFF_7, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF7 */ > + { STB0899_OFF8_EQ_Q_INIT_COEFF_8, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF8 */ > + { STB0899_OFF9_EQ_Q_INIT_COEFF_9, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF9 */ > + { STB0899_OFFa_EQ_Q_INIT_COEFF_10,STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF10*/ > + { STB0899_OFF0_EQ_I_OUT_COEFF_0 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT0 */ > + { STB0899_OFF1_EQ_I_OUT_COEFF_1 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT1 */ > + { STB0899_OFF2_EQ_I_OUT_COEFF_2 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT2 */ > + { STB0899_OFF3_EQ_I_OUT_COEFF_3 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT3 */ > + { STB0899_OFF4_EQ_I_OUT_COEFF_4 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT4 */ > + { STB0899_OFF5_EQ_I_OUT_COEFF_5 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT5 */ > + { STB0899_OFF6_EQ_I_OUT_COEFF_6 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT6 */ > + { STB0899_OFF7_EQ_I_OUT_COEFF_7 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT7 */ > + { STB0899_OFF8_EQ_I_OUT_COEFF_8 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT8 */ > + { STB0899_OFF9_EQ_I_OUT_COEFF_9 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT9 */ > + { STB0899_OFFa_EQ_I_OUT_COEFF_10,STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT10*/ > + { STB0899_OFF0_EQ_Q_OUT_COEFF_0 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT0 */ > + { STB0899_OFF1_EQ_Q_OUT_COEFF_1 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT1 */ > + { STB0899_OFF2_EQ_Q_OUT_COEFF_2 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT2 */ > + { STB0899_OFF3_EQ_Q_OUT_COEFF_3 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT3 */ > + { STB0899_OFF4_EQ_Q_OUT_COEFF_4 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT4 */ > + { STB0899_OFF5_EQ_Q_OUT_COEFF_5 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT5 */ > + { STB0899_OFF6_EQ_Q_OUT_COEFF_6 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT6 */ > + { STB0899_OFF7_EQ_Q_OUT_COEFF_7 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT7 */ > + { STB0899_OFF8_EQ_Q_OUT_COEFF_8 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT8 */ > + { STB0899_OFF9_EQ_Q_OUT_COEFF_9 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT9 */ > + { STB0899_OFFa_EQ_Q_OUT_COEFF_10, STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT10*/ > + { 0xffff , 0xffffffff , 0xffffffff }, > +}; > + > +static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = { > + { STB0899_DEMOD , 0x00 }, > + { STB0899_RCOMPC , 0xc9 }, > + { STB0899_AGC1CN , 0x41 }, > + { STB0899_AGC1REF , 0x10 }, > + { STB0899_RTC , 0x7a }, > + { STB0899_TMGCFG , 0x4e }, > + { STB0899_AGC2REF , 0x34 }, > + { STB0899_TLSR , 0x84 }, > + { STB0899_CFD , 0xc7 }, > + { STB0899_ACLC , 0x87 }, > + { STB0899_BCLC , 0x94 }, > + { STB0899_EQON , 0x41 }, > + { STB0899_LDT , 0xdd }, > + { STB0899_LDT2 , 0xc9 }, > + { STB0899_EQUALREF , 0xb4 }, > + { STB0899_TMGRAMP , 0x10 }, > + { STB0899_TMGTHD , 0x30 }, > + { STB0899_IDCCOMP , 0xfb }, > + { STB0899_QDCCOMP , 0x03 }, > + { STB0899_POWERI , 0x3b }, > + { STB0899_POWERQ , 0x3d }, > + { STB0899_RCOMP , 0x81 }, > + { STB0899_AGCIQIN , 0x80 }, > + { STB0899_AGC2I1 , 0x04 }, > + { STB0899_AGC2I2 , 0xf5 }, > + { STB0899_TLIR , 0x25 }, > + { STB0899_RTF , 0x80 }, > + { STB0899_DSTATUS , 0x00 }, > + { STB0899_LDI , 0xca }, > + { STB0899_CFRM , 0xf1 }, > + { STB0899_CFRL , 0xf3 }, > + { STB0899_NIRM , 0x2a }, > + { STB0899_NIRL , 0x05 }, > + { STB0899_ISYMB , 0x17 }, > + { STB0899_QSYMB , 0xfa }, > + { STB0899_SFRH , 0x2f }, > + { STB0899_SFRM , 0x68 }, > + { STB0899_SFRL , 0x40 }, > + { STB0899_SFRUPH , 0x2f }, > + { STB0899_SFRUPM , 0x68 }, > + { STB0899_SFRUPL , 0x40 }, > + { STB0899_EQUAI1 , 0xfd }, > + { STB0899_EQUAQ1 , 0x04 }, > + { STB0899_EQUAI2 , 0x0f }, > + { STB0899_EQUAQ2 , 0xff }, > + { STB0899_EQUAI3 , 0xdf }, > + { STB0899_EQUAQ3 , 0xfa }, > + { STB0899_EQUAI4 , 0x37 }, > + { STB0899_EQUAQ4 , 0x0d }, > + { STB0899_EQUAI5 , 0xbd }, > + { STB0899_EQUAQ5 , 0xf7 }, > + { STB0899_DSTATUS2 , 0x00 }, > + { STB0899_VSTATUS , 0x00 }, > + { STB0899_VERROR , 0xff }, > + { STB0899_IQSWAP , 0x2a }, > + { STB0899_ECNT1M , 0x00 }, > + { STB0899_ECNT1L , 0x00 }, > + { STB0899_ECNT2M , 0x00 }, > + { STB0899_ECNT2L , 0x00 }, > + { STB0899_ECNT3M , 0x00 }, > + { STB0899_ECNT3L , 0x00 }, > + { STB0899_FECAUTO1 , 0x06 }, > + { STB0899_FECM , 0x01 }, > + { STB0899_VTH12 , 0xf0 }, > + { STB0899_VTH23 , 0xa0 }, > + { STB0899_VTH34 , 0x78 }, > + { STB0899_VTH56 , 0x4e }, > + { STB0899_VTH67 , 0x48 }, > + { STB0899_VTH78 , 0x38 }, > + { STB0899_PRVIT , 0xff }, > + { STB0899_VITSYNC , 0x19 }, > + { STB0899_RSULC , 0xb1 }, // DVB = 0xb1, DSS = 0xa1 > + { STB0899_TSULC , 0x42 }, > + { STB0899_RSLLC , 0x40 }, > + { STB0899_TSLPL , 0x12 }, > + { STB0899_TSCFGH , 0x0c }, //0x0c > + { STB0899_TSCFGM , 0x00 }, > + { STB0899_TSCFGL , 0x0c }, //0x0c > + { STB0899_TSOUT , 0x07 }, > + { STB0899_RSSYNCDEL , 0x00 }, > + { STB0899_TSINHDELH , 0x02 }, > + { STB0899_TSINHDELM , 0x00 }, > + { STB0899_TSINHDELL , 0x00 }, > + { STB0899_TSLLSTKM , 0x00 }, > + { STB0899_TSLLSTKL , 0x00 }, > + { STB0899_TSULSTKM , 0x00 }, > + { STB0899_TSULSTKL , 0xab }, > + { STB0899_PCKLENUL , 0x00 }, > + { STB0899_PCKLENLL , 0xcc }, > + { STB0899_RSPCKLEN , 0xcc }, > + { STB0899_TSSTATUS , 0x80 }, > + { STB0899_ERRCTRL1 , 0xb6 }, > + { STB0899_ERRCTRL2 , 0x96 }, > + { STB0899_ERRCTRL3 , 0x89 }, > + { STB0899_DMONMSK1 , 0x27 }, > + { STB0899_DMONMSK0 , 0x03 }, > + { STB0899_DEMAPVIT , 0x5c }, > + { STB0899_PLPARM , 0x1f }, > + { STB0899_PDELCTRL , 0x48 }, > + { STB0899_PDELCTRL2 , 0x00 }, > + { STB0899_BBHCTRL1 , 0x00 }, > + { STB0899_BBHCTRL2 , 0x00 }, > + { STB0899_HYSTTHRESH , 0x77 }, > + { STB0899_MATCSTM , 0x00 }, > + { STB0899_MATCSTL , 0x00 }, > + { STB0899_UPLCSTM , 0x00 }, > + { STB0899_UPLCSTL , 0x00 }, > + { STB0899_DFLCSTM , 0x00 }, > + { STB0899_DFLCSTL , 0x00 }, > + { STB0899_SYNCCST , 0x00 }, > + { STB0899_SYNCDCSTM , 0x00 }, > + { STB0899_SYNCDCSTL , 0x00 }, > + { STB0899_ISI_ENTRY , 0x00 }, > + { STB0899_ISI_BIT_EN , 0x00 }, > + { STB0899_MATSTRM , 0x00 }, > + { STB0899_MATSTRL , 0x00 }, > + { STB0899_UPLSTRM , 0x00 }, > + { STB0899_UPLSTRL , 0x00 }, > + { STB0899_DFLSTRM , 0x00 }, > + { STB0899_DFLSTRL , 0x00 }, > + { STB0899_SYNCSTR , 0x00 }, > + { STB0899_SYNCDSTRM , 0x00 }, > + { STB0899_SYNCDSTRL , 0x00 }, > + { STB0899_CFGPDELSTATUS1 , 0x10 }, > + { STB0899_CFGPDELSTATUS2 , 0x00 }, > + { STB0899_BBFERRORM , 0x00 }, > + { STB0899_BBFERRORL , 0x00 }, > + { STB0899_UPKTERRORM , 0x00 }, > + { STB0899_UPKTERRORL , 0x00 }, > + { 0xffff , 0xff }, > +}; > + > +static const struct stb0899_s2_reg tt3200_stb0899_s2_init_4[] = { > + { STB0899_OFF0_BLOCK_LNGTH , STB0899_BASE_BLOCK_LNGTH , 0x00000008 }, /* BLOCKLNGTH */ > + { STB0899_OFF0_ROW_STR , STB0899_BASE_ROW_STR , 0x000000b4 }, /* ROWSTR */ > + { STB0899_OFF0_BN_END_ADDR , STB0899_BASE_BN_END_ADDR , 0x000004b5 }, /* BNANDADDR */ > + { STB0899_OFF0_CN_END_ADDR , STB0899_BASE_CN_END_ADDR , 0x00000b4b }, /* CNANDADDR */ > + { STB0899_OFF0_INFO_LENGTH , STB0899_BASE_INFO_LENGTH , 0x00000078 }, /* INFOLENGTH */ > + { STB0899_OFF0_BOT_ADDR , STB0899_BASE_BOT_ADDR , 0x000001e0 }, /* BOT_ADDR */ > + { STB0899_OFF0_BCH_BLK_LN , STB0899_BASE_BCH_BLK_LN , 0x0000a8c0 }, /* BCHBLKLN */ > + { STB0899_OFF0_BCH_T , STB0899_BASE_BCH_T , 0x0000000c }, /* BCHT */ > + { STB0899_OFF0_CNFG_MODE , STB0899_BASE_CNFG_MODE , 0x00000001 }, /* CNFGMODE */ > + { STB0899_OFF0_LDPC_STAT , STB0899_BASE_LDPC_STAT , 0x0000000d }, /* LDPCSTAT */ > + { STB0899_OFF0_ITER_SCALE , STB0899_BASE_ITER_SCALE , 0x00000040 }, /* ITERSCALE */ > + { STB0899_OFF0_INPUT_MODE , STB0899_BASE_INPUT_MODE , 0x00000000 }, /* INPUTMODE */ > + { STB0899_OFF0_LDPCDECRST , STB0899_BASE_LDPCDECRST , 0x00000000 }, /* LDPCDECRST */ > + { STB0899_OFF0_CLK_PER_BYTE_RW , STB0899_BASE_CLK_PER_BYTE_RW , 0x00000008 }, /* CLKPERBYTE */ > + { STB0899_OFF0_BCH_ERRORS , STB0899_BASE_BCH_ERRORS , 0x00000000 }, /* BCHERRORS */ > + { STB0899_OFF0_LDPC_ERRORS , STB0899_BASE_LDPC_ERRORS , 0x00000000 }, /* LDPCERRORS */ > + { STB0899_OFF0_BCH_MODE , STB0899_BASE_BCH_MODE , 0x00000000 }, /* BCHMODE */ > + { STB0899_OFF0_ERR_ACC_PER , STB0899_BASE_ERR_ACC_PER , 0x00000008 }, /* ERRACCPER */ > + { STB0899_OFF0_BCH_ERR_ACC , STB0899_BASE_BCH_ERR_ACC , 0x00000000 }, /* BCHERRACC */ > + { STB0899_OFF0_FEC_TP_SEL , STB0899_BASE_FEC_TP_SEL , 0x00000000 }, /* FECTPSEL */ > + { 0xffff , 0xffffffff , 0xffffffff }, > +}; > + > +static const struct stb0899_s1_reg tt3200_stb0899_s1_init_5[] = { > + { STB0899_TSTCK , 0x00 }, > + { STB0899_TSTRES , 0x00 }, > + { STB0899_TSTOUT , 0x00 }, > + { STB0899_TSTIN , 0x00 }, > + { STB0899_TSTSYS , 0x00 }, > + { STB0899_TSTCHIP , 0x00 }, > + { STB0899_TSTFREE , 0x00 }, > + { STB0899_TSTI2C , 0x00 }, > + { STB0899_BITSPEEDM , 0x00 }, > + { STB0899_BITSPEEDL , 0x00 }, > + { STB0899_TBUSBIT , 0x00 }, > + { STB0899_TSTDIS , 0x00 }, > + { STB0899_TSTDISRX , 0x00 }, > + { STB0899_TSTJETON , 0x00 }, > + { STB0899_TSTDCADJ , 0x00 }, > + { STB0899_TSTAGC1 , 0x00 }, > + { STB0899_TSTAGC1N , 0x00 }, > + { STB0899_TSTPOLYPH , 0x00 }, > + { STB0899_TSTR , 0x00 }, > + { STB0899_TSTAGC2 , 0x00 }, > + { STB0899_TSTCTL1 , 0x00 }, > + { STB0899_TSTCTL2 , 0x00 }, > + { STB0899_TSTCTL3 , 0x00 }, > + { STB0899_TSTDEMAP , 0x00 }, > + { STB0899_TSTDEMAP2 , 0x00 }, > + { STB0899_TSTDEMMON , 0x00 }, > + { STB0899_TSTRATE , 0x00 }, > + { STB0899_TSTSELOUT , 0x00 }, > + { STB0899_TSYNC , 0x00 }, > + { STB0899_TSTERR , 0x00 }, > + { STB0899_TSTRAM1 , 0x00 }, > + { STB0899_TSTVSELOUT , 0x00 }, > + { STB0899_TSTFORCEIN , 0x00 }, > + { STB0899_TSTRS1 , 0x00 }, > + { STB0899_TSTRS2 , 0x00 }, > + { STB0899_TSTRS3 , 0x00 }, > + { STB0899_GHOSTREG , 0x81 }, > + { 0xffff , 0xff }, > +}; > + > +#define KNC1_DVBS2_ESNO_AVE 3 > +#define KNC1_DVBS2_ESNO_QUANT 32 > +#define KNC1_DVBS2_AVFRAMES_COARSE 10 > +#define KNC1_DVBS2_AVFRAMES_FINE 20 > +#define KNC1_DVBS2_MISS_THRESHOLD 6 > +#define KNC1_DVBS2_UWP_THRESHOLD_ACQ 1125 > +#define KNC1_DVBS2_UWP_THRESHOLD_TRACK 758 > +#define KNC1_DVBS2_UWP_THRESHOLD_SOF 1350 > +#define KNC1_DVBS2_SOF_SEARCH_TIMEOUT 1664100 > + > +#define KNC1_DVBS2_BTR_NCO_BITS 28 > +#define KNC1_DVBS2_BTR_GAIN_SHIFT_OFFSET 15 > +#define KNC1_DVBS2_CRL_NCO_BITS 30 > +#define KNC1_DVBS2_LDPC_MAX_ITER 70 > + > +static struct stb0899_config tt3200_config = { > + .init_dev = tt3200_stb0899_s1_init_1, > + .init_s2_demod = tt3200_stb0899_s2_init_2, > + .init_s1_demod = tt3200_stb0899_s1_init_3, > + .init_s2_fec = tt3200_stb0899_s2_init_4, > + .init_tst = tt3200_stb0899_s1_init_5, > + > + .demod_address = 0x68, > +// .ts_output_mode = STB0899_OUT_PARALLEL, /* types = SERIAL/PARALLEL */ > + .block_sync_mode = STB0899_SYNC_FORCED, /* DSS, SYNC_FORCED/UNSYNCED */ > +// .ts_pfbit_toggle = STB0899_MPEG_NORMAL, /* DirecTV, MPEG toggling seq */ > + > + .xtal_freq = 27000000, > + .inversion = 1, > + > + .esno_ave = KNC1_DVBS2_ESNO_AVE, > + .esno_quant = KNC1_DVBS2_ESNO_QUANT, > + .avframes_coarse = KNC1_DVBS2_AVFRAMES_COARSE, > + .avframes_fine = KNC1_DVBS2_AVFRAMES_FINE, > + .miss_threshold = KNC1_DVBS2_MISS_THRESHOLD, > + .uwp_threshold_acq = KNC1_DVBS2_UWP_THRESHOLD_ACQ, > + .uwp_threshold_track = KNC1_DVBS2_UWP_THRESHOLD_TRACK, > + .uwp_threshold_sof = KNC1_DVBS2_UWP_THRESHOLD_SOF, > + .sof_search_timeout = KNC1_DVBS2_SOF_SEARCH_TIMEOUT, > + > + .btr_nco_bits = KNC1_DVBS2_BTR_NCO_BITS, > + .btr_gain_shift_offset = KNC1_DVBS2_BTR_GAIN_SHIFT_OFFSET, > + .crl_nco_bits = KNC1_DVBS2_CRL_NCO_BITS, > + .ldpc_max_iter = KNC1_DVBS2_LDPC_MAX_ITER, > +}; > + > +struct stb6100_config tt3200_stb6100_config = { > + .tuner_address = 0x60 > +}; > + > + > > static void frontend_init(struct budget_ci *budget_ci) > { > @@ -1156,6 +1682,32 @@ static void frontend_init(struct budget_ > } > > break; > + > + case 0x1019: // TT S2-3200 PCI > + budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap); > + if (budget_ci->budget.dvb_frontend) { > + if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) { > + > + tt3200_config.tuner_set_frequency = budget_ci->budget.dvb_frontend->ops.tuner_ops.set_frequency; > + tt3200_config.tuner_get_frequency = budget_ci->budget.dvb_frontend->ops.tuner_ops.get_frequency; > + tt3200_config.tuner_set_bandwidth = budget_ci->budget.dvb_frontend->ops.tuner_ops.set_bandwidth; > + tt3200_config.tuner_get_bandwidth = budget_ci->budget.dvb_frontend->ops.tuner_ops.get_bandwidth; > + > + if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) { > + printk("%s: No LNBP21 found!\n", __FUNCTION__); > + if (budget_ci->budget.dvb_frontend->ops.tuner_ops.release) > + budget_ci->budget.dvb_frontend->ops.tuner_ops.release(budget_ci->budget.dvb_frontend); > + dvb_frontend_detach(budget_ci->budget.dvb_frontend); > + budget_ci->budget.dvb_frontend = NULL; > + } > + } else { > + printk("%s: No STB6100 found!\n", __FUNCTION__); > + dvb_frontend_detach(budget_ci->budget.dvb_frontend); > + budget_ci->budget.dvb_frontend = NULL; > + } > + } > + break; > + > } > > if (budget_ci->budget.dvb_frontend == NULL) { > @@ -1244,6 +1796,7 @@ MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV > MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT); > MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT); > MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT); > +MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT); > > static struct pci_device_id pci_tbl[] = { > MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c), > @@ -1252,6 +1805,7 @@ static struct pci_device_id pci_tbl[] = > MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011), > MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012), > MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017), > + MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019), > { > .vendor = 0, > } > diff -urNp v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget.h v4l-dvb/linux/drivers/media/dvb/ttpci/budget.h > --- v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget.h 2007-02-24 13:07:53.000000000 +0100 > +++ v4l-dvb/linux/drivers/media/dvb/ttpci/budget.h 2007-05-06 20:18:22.000000000 +0200 > @@ -108,6 +108,7 @@ static struct saa7146_pci_extension_data > #define BUDGET_KNC1TP 13 > #define BUDGET_TVSTAR 14 > #define BUDGET_KNC1S2 15 > +#define BUDGET_TT3200 16 > > #define BUDGET_VIDEO_PORTA 0 > #define BUDGET_VIDEO_PORTB 1 > > > ------------------------------------------------------------------------ > > _______________________________________________ > linux-dvb mailing list > linux-dvb@xxxxxxxxxxx > http://www.linuxtv.org/cgi-bin/mailman/listinfo/linux-dvb
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