On Tue, 13 Mar 2007, Hartmut Hackmann wrote:
> > I think that should be done is adjust the IF values in in the dvb-pll
> > config structs to NOT include step-size/2 for rounding. Just use the IF
> > frequency. This is how most of the PLL definitions are already. The code
> > which calculates the divisor should be changed to round to the nearest
> > integer, rather than round down.
> >
> Jep
I've made patches to do this, I'll send them to the list later.
> > philips_fmd1216_tuner_init() just sends { 0x0b, 0xdc, 0x9c, 0xa0 } to the
> > tuner. It could be replaced with the dvb-pll version, which will have
> > the same effect.
> >
> I will have a look
My fmd1216 patch will have the tuner init function send {0xdd, 0xa0} to the
tuner. That will set the agc value (byte AB) to 0xa0, the same thing.
> > after _module loading_ it will send {0x0b, 0xdc, 0x9c, 0x60} and then
> > {0x0b, 0xdc, 0x86, 0x54} to the tuner. The first sequence sets AGC to
> > analog mode (IMHO, the v4l tuner driver should do this for tuner init,
> > but it doesn't). The second sequence just tunes to some random frequency
> > for no apparent reason. Neither actually turns the tuner off!
> >
> AFIK the v4l tuner driver can't do this since init is called only one at
> module initialization. Maybe the sequence is overdone but the intention is:
Yeah, V4L should do it, but doesn't. I think there is a special case hack
for some tuners where on every tune, they take the 4-byte command, send it
once, then modify the last two bytes to set AGC, and then send it again.
> - set up RF AGC
> - set the PLL to a valid frequency. I was told that this is important.
If you just send two bytes, then it's not necessary to change the frequency
from what it was at before.
Anyway, I don't think the frequency is valid either:
divisor = 0x0bdc, ratio bits = 1,1 = 62.5 kHz, so freq = 189.75 MHz
But, BB = 0x54, which is analog mode HIGH band. 189.75 MHz would be in the
LOW band. (remember to subtract the IF frequency to compare to the
bandswitch points used in the code)
> - turn on the tda9887. This is invisible on the I2C bus in DVB mode.
How does that happen? I figured P4 just changed the SAW filters, but it
enables/disables the tda9887 too?
> I am not aware that the tuner actually has a sleep mode. I used the sleep
> call be cause it simply was there.
If you set the low bit of CB, it disables the tuning voltage. That's
probably the closest thing to sleep mode there is.
> > I think this could be replaced with the dvb-pll sleep function, if a
> > sleep sequence was added to dvb_pll_fmd1216me. We should send {0x9d,
> > 0x60}, which will turn the tuner off and set the AGC back to the analog
> > recommended value.
> >
> Hm, the sequence is incomplete.. Do you have more information about the
> PLL chip?
The documentation for the Infineon TUA6034 should be easy to find if you
don't have it. It's pretty clear that you don't need to send the divisor
bytes each time. You can just send CB+BB or in this case CB+AB. And I've
verified that indeed you can set the AGC values with just two bytes.
> Are you aware that there is also the td1316?
One tuner at a time....
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