Edgar Toernig wrote: >Manu Abraham wrote: > > >>>I still don't know what causes the audio fifo to overflow >>>on some chipsets - the video fifo seems to never show >>>this problem (yeah, it's two time as big but the data >>>rate is much more then twice of that comming via DVB). >>> >>> >>The reason why it overflows is data is not read from the FIFO as it >>should be and the PCI bus expects larger chunks. Another way of handling >>this is to reduce the latency, [...] >> >> > >All good and fine - but I get no errors with the video fifo, >only with the audio fifo. Afaics, there are only two differences: >the video fifo is two times as deep as the audio fifo (but data rates >are 4-8 times as high), and the read-only MAX_LAT register which is >10us for video and 64us for audio. > > > Yeah, that shouldn't happen. Why don't you try grabbing the entire stream as it is from the buffer. This should be almost the same as the transfer from the video fifo. At least that could help in identifying the problem. > > >>But anyway what's the idea behind reducing the fifo size if in case of >>errors ? normally when we have communication errors , we generally >>increase the buffer size, not reduce it... >> >> > >Not the fifo-depth is changed (that's not possible in the bt878), the >trigger point at which access to the PCI bus is requested is lowered. > > > Changing the trigger point is indirectly having the same effect as that of the buffer size, even though directly it is not handling the buffer size. Manu
