The op_sync_orin and irq_err_ignore code is not really card
specific. Some cards set op_sync_orin but any card would
benefit from setting it. And irq_err_ignore just shuts up
some error printks in the irq handler.
This patch activates resyncing for all cards thus making
op_sync_orin superfluous.
irq_err_ignore is removed. The error printks are only
activated then debugging is turned on.
---
bt878.c | 30 +++++++++-------------------
bt878.h | 5 ----
dvb-bt8xx.c | 55 ++++++----------------------------------------------
dvb-bt8xx.h | 2 -
4 files changed, 18 insertions(+), 74 deletions(-)
--- 0.3/drivers/media/dvb/bt8xx/dvb-bt8xx.h Sat, 07 Jan 2006 00:06:16 +0100 froese (kernel-dvb/h/8_dvb-bt8xx. 1.1 644)
+++ 0.4/drivers/media/dvb/bt8xx/dvb-bt8xx.h Sat, 07 Jan 2006 02:03:06 +0100 froese (kernel-dvb/h/8_dvb-bt8xx. 1.2 644)
@@ -49,8 +49,6 @@
struct dmx_frontend fe_hw;
struct dmx_frontend fe_mem;
u32 gpio_mode;
- u32 op_sync_orin;
- u32 irq_err_ignore;
struct i2c_adapter *i2c_adapter;
struct dvb_net dvbnet;
--- 0.3/drivers/media/dvb/bt8xx/dvb-bt8xx.c Sat, 07 Jan 2006 01:12:16 +0100 froese (kernel-dvb/h/9_dvb-bt8xx. 1.3 644)
+++ 0.4/drivers/media/dvb/bt8xx/dvb-bt8xx.c Sat, 07 Jan 2006 02:03:06 +0100 froese (kernel-dvb/h/9_dvb-bt8xx. 1.4 644)
@@ -78,8 +78,7 @@
card->nfeeds++;
rc = card->nfeeds;
if (card->nfeeds == 1)
- bt878_start(card->bt, card->gpio_mode,
- card->op_sync_orin, card->irq_err_ignore);
+ bt878_start(card->bt, card->gpio_mode);
up(&card->lock);
return rc;
}
@@ -816,73 +815,33 @@
switch(sub->core->type) {
case BTTV_BOARD_PINNACLESAT:
- card->gpio_mode = 0x0400c060;
- /* should be: BT878_A_GAIN=0,BT878_A_PWRDN,BT878_DA_DPM,BT878_DA_SBR,
- BT878_DA_IOM=1,BT878_DA_APP to enable serial highspeed mode. */
- card->op_sync_orin = 0;
- card->irq_err_ignore = 0;
- break;
-
-#ifdef BTTV_BOARD_DVICO_DVBT_LITE
case BTTV_BOARD_DVICO_DVBT_LITE:
-#endif
- card->gpio_mode = 0x0400C060;
- card->op_sync_orin = 0;
- card->irq_err_ignore = 0;
- /* 26, 15, 14, 6, 5
- * A_PWRDN DA_DPM DA_SBR DA_IOM_DA
- * DA_APP(parallel) */
- break;
-
-#ifdef BTTV_BOARD_DVICO_FUSIONHDTV_5_LITE
case BTTV_BOARD_DVICO_FUSIONHDTV_5_LITE:
-#endif
- card->gpio_mode = 0x0400c060;
- card->op_sync_orin = BT878_RISC_SYNC_MASK;
- card->irq_err_ignore = BT878_AFBUS | BT878_AFDSR;
+ card->gpio_mode = 0x0400c060; /* high speed serial mode */
break;
-#ifdef BTTV_BOARD_TWINHAN_VP3021
- case BTTV_BOARD_TWINHAN_VP3021:
-#else
case BTTV_BOARD_NEBULA_DIGITV:
-#endif
case BTTV_BOARD_AVDVBT_761:
- card->gpio_mode = (1 << 26) | (1 << 14) | (1 << 5);
- card->op_sync_orin = 0;
- card->irq_err_ignore = 0;
- /* A_PWRDN DA_SBR DA_APP (high speed serial) */
- break;
-
case BTTV_BOARD_AVDVBT_771: //case 0x07711461:
- card->gpio_mode = 0x0400402B;
- card->op_sync_orin = BT878_RISC_SYNC_MASK;
- card->irq_err_ignore = 0;
- /* A_PWRDN DA_SBR DA_APP[0] PKTP=10 RISC_ENABLE FIFO_ENABLE*/
+ card->gpio_mode = 0x04004020; /* parallel mode */
break;
case BTTV_BOARD_TWINHAN_DST:
- card->gpio_mode = 0x2204f2c;
- card->op_sync_orin = BT878_RISC_SYNC_MASK;
- card->irq_err_ignore = BT878_APABORT | BT878_ARIPERR |
- BT878_APPERR | BT878_AFBUS;
+ card->gpio_mode = 0x2204f20;
/* 25,21,14,11,10,9,8,3,2 then
* 0x33 = 5,4,1,0
* A_SEL=SML, DA_MLB, DA_SBR,
- * DA_SDR=f, fifo trigger = 32 DWORDS
+ * DA_SDR=f,
* IOM = 0 == audio A/D
* DPM = 0 == digital audio mode
* == async data parallel port
* then 0x33 (13 is set by start_capture)
* DA_APP = async data parallel port,
- * ACAP_EN = 1,
- * RISC+FIFO ENABLE */
+ */
break;
case BTTV_BOARD_PC_HDTV:
- card->gpio_mode = 0x0100EC7B;
- card->op_sync_orin = 0;
- card->irq_err_ignore = 0;
+ card->gpio_mode = 0x0100EC60;
break;
default:
--- 0.3/drivers/media/dvb/bt8xx/bt878.h Sat, 07 Jan 2006 00:06:16 +0100 froese (kernel-dvb/h/15_bt878.h 1.1 644)
+++ 0.4/drivers/media/dvb/bt8xx/bt878.h Sat, 07 Jan 2006 02:03:06 +0100 froese (kernel-dvb/h/15_bt878.h 1.2 644)
@@ -86,8 +86,6 @@
#define BT878_MAX 4
-#define BT878_RISC_SYNC_MASK (1 << 15)
-
extern int bt878_num;
struct bt878 {
@@ -125,8 +123,7 @@
extern struct bt878 bt878[BT878_MAX];
-void bt878_start(struct bt878 *bt, u32 controlreg, u32 op_sync_orin,
- u32 irq_err_ignore);
+void bt878_start(struct bt878 *bt, u32 controlreg);
void bt878_stop(struct bt878 *bt);
#if defined(__powerpc__) /* big-endian */
--- 0.3/drivers/media/dvb/bt8xx/bt878.c Sat, 07 Jan 2006 00:53:31 +0100 froese (kernel-dvb/h/16_bt878.c 1.2 644)
+++ 0.4/drivers/media/dvb/bt8xx/bt878.c Sat, 07 Jan 2006 02:03:06 +0100 froese (kernel-dvb/h/16_bt878.c 1.3 644)
@@ -165,13 +165,13 @@
}
-static void bt878_risc_program(struct bt878 *bt, u32 op_sync_orin)
+static void bt878_risc_program(struct bt878 *bt)
{
u32 buf_pos = 0;
u32 line;
RISC_FLUSH();
- RISC_INSTR(RISC_SYNC | RISC_SYNC_FM1 | op_sync_orin);
+ RISC_INSTR(RISC_SYNC | RISC_SYNC_FM1 | RISC_SYNC_RESYNC);
RISC_INSTR(0);
dprintk("bt878: risc len lines %u, bytes per line %u\n",
@@ -194,7 +194,7 @@
buf_pos += bt->line_bytes;
}
- RISC_INSTR(RISC_SYNC | op_sync_orin | RISC_SYNC_VRO);
+ RISC_INSTR(RISC_SYNC | RISC_SYNC_RESYNC | RISC_SYNC_VRO);
RISC_INSTR(0);
RISC_INSTR(RISC_JUMP);
@@ -207,8 +207,7 @@
/* Start/Stop grabbing funcs */
/*****************************/
-void bt878_start(struct bt878 *bt, u32 controlreg, u32 op_sync_orin,
- u32 irq_err_ignore)
+void bt878_start(struct bt878 *bt, u32 controlreg)
{
u32 int_mask;
@@ -216,26 +215,17 @@
/* complete the writing of the risc dma program now we have
* the card specifics
*/
- bt878_risc_program(bt, op_sync_orin);
+ bt878_risc_program(bt);
controlreg &= ~0x1f;
controlreg |= 0x1b;
btwrite(bt->risc_dma, BT878_ARISC_START);
- /* original int mask had :
- * 6 2 8 4 0
- * 1111 1111 1000 0000 0000
- * SCERR|OCERR|PABORT|RIPERR|FDSR|FTRGT|FBUS|RISCI
- * Hacked for DST to:
- * SCERR | OCERR | FDSR | FTRGT | FBUS | RISCI
- */
- int_mask = BT878_ASCERR | BT878_AOCERR | BT878_APABORT |
- BT878_ARIPERR | BT878_APPERR | BT878_AFDSR | BT878_AFTRGT |
- BT878_AFBUS | BT878_ARISCI;
-
-
- /* ignore pesky bits */
- int_mask &= ~irq_err_ignore;
+ int_mask = BT878_ARISCI;
+ if (bt878_debug)
+ int_mask |= BT878_ASCERR | BT878_AOCERR |
+ BT878_APABORT | BT878_ARIPERR | BT878_APPERR |
+ BT878_AFDSR | BT878_AFTRGT | BT878_AFBUS;
btwrite(int_mask, BT878_AINT_MASK);
btwrite(controlreg, BT878_AGPIO_DMA_CTL);
