Re: [PATCH v2 1/5] staging: wilc1000: Last line is empty

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On Tue, May 02, 2017 at 04:18:39PM +0200, Vincent Siles wrote:
> Removing empty line at the end of the file

Hi Vincent,

Small comment on your patch series. You may have more success if your
summary phrase is in imperative mood i.e sounds like you are
commanding changes to be made to the code base

Recent examples from LKML

fpga manager: Add Altera CvP driver
sched/fair: fix load balancer behavior when cgroup is in use

Aslo the changelog should describe the reason for the patch and then
describe the changes made in the patch to rectify the previously
described problem. See Documentation/process/submitting-patches.rst
for complete description of how to write a changelog.

Good luck,
Tobin.
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