On 02/17/2017 06:16 AM, Philipp Zabel wrote:
On Fri, 2017-02-17 at 11:47 +0100, Philipp Zabel wrote:
On Wed, 2017-02-15 at 18:19 -0800, Steve Longerbeam wrote:
+static void csi2_dphy_init(struct csi2_dev *csi2)
+{
+ /*
+ * FIXME: 0x14 is derived from a fixed D-PHY reference
+ * clock from the HSI_TX PLL, and a fixed target lane max
+ * bandwidth of 300 Mbps. This value should be derived
If the table in https://community.nxp.com/docs/DOC-94312 is correct,
this should be 850 Mbps. Where does this 300 Mbps value come from?
I got it, the dptdin_map value for 300 Mbps is 0x14 in the Rockchip DSI
driver. But that value is written to the register as HSFREQRANGE_SEL(x):
#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
Ah you are right, 0x14 would be a "testdin" value of 0x0a, which from
the Rockchip table would be 950 MHz per lane.
But thanks for pointing the table at
https://community.nxp.com/docs/DOC-94312. That table is what
should be referenced in the above comment (850 MHz per lane
for a 27MHz reference clock). I will update the comment based
on that table.
Steve
which is 0x28. Further, the Rockchip D-PHY probably is another version,
as its max_mbps goes up to 1500.
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