Fix the checkpatch.pl issues: CHECK: Prefer using the BIT macro Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx> Cc: Ian Abbott <abbotti@xxxxxxxxx> Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/staging/comedi/drivers/z8536.h | 89 ++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 41 deletions(-) diff --git a/drivers/staging/comedi/drivers/z8536.h b/drivers/staging/comedi/drivers/z8536.h index 7be5310..47eadbf 100644 --- a/drivers/staging/comedi/drivers/z8536.h +++ b/drivers/staging/comedi/drivers/z8536.h @@ -24,11 +24,12 @@ #define Z8536_CFG_CTRL_PCE_CT3E BIT(4) /* Port C & C/T 3 Enable */ #define Z8536_CFG_CTRL_PLC BIT(3) /* Port A/B Link Control */ #define Z8536_CFG_CTRL_PAE BIT(2) /* Port A Enable */ -#define Z8536_CFG_CTRL_LC_INDEP (0 << 0)/* C/Ts Independent */ -#define Z8536_CFG_CTRL_LC_GATE (1 << 0)/* C/T 1 Out Gates C/T 2 */ -#define Z8536_CFG_CTRL_LC_TRIG (2 << 0)/* C/T 1 Out Triggers C/T 2 */ -#define Z8536_CFG_CTRL_LC_CLK (3 << 0)/* C/T 1 Out Clocks C/T 2 */ -#define Z8536_CFG_CTRL_LC_MASK (3 << 0)/* C/T Link Control mask */ +#define Z8536_CFG_CTRL_LC(x) (((x) & 0x3) << 0) /* Link Control */ +#define Z8536_CFG_CTRL_LC_INDEP Z8536_CFG_CTRL_LC(0)/* Independent */ +#define Z8536_CFG_CTRL_LC_GATE Z8536_CFG_CTRL_LC(1)/* 1 Gates 2 */ +#define Z8536_CFG_CTRL_LC_TRIG Z8536_CFG_CTRL_LC(2)/* 1 Triggers 2 */ +#define Z8536_CFG_CTRL_LC_CLK Z8536_CFG_CTRL_LC(3)/* 1 Clocks 2 */ +#define Z8536_CFG_CTRL_LC_MASK Z8536_CFG_CTRL_LC(3) /* Interrupt Vector registers */ #define Z8536_PA_INT_VECT_REG 0x02 @@ -43,15 +44,16 @@ #define Z8536_CT2_CMDSTAT_REG 0x0b #define Z8536_CT3_CMDSTAT_REG 0x0c #define Z8536_CT_CMDSTAT_REG(x) (0x0a + (x)) -#define Z8536_CMD_NULL (0 << 5)/* Null Code */ -#define Z8536_CMD_CLR_IP_IUS (1 << 5)/* Clear IP & IUS */ -#define Z8536_CMD_SET_IUS (2 << 5)/* Set IUS */ -#define Z8536_CMD_CLR_IUS (3 << 5)/* Clear IUS */ -#define Z8536_CMD_SET_IP (4 << 5)/* Set IP */ -#define Z8536_CMD_CLR_IP (5 << 5)/* Clear IP */ -#define Z8536_CMD_SET_IE (6 << 5)/* Set IE */ -#define Z8536_CMD_CLR_IE (7 << 5)/* Clear IE */ -#define Z8536_CMD_MASK (7 << 5) +#define Z8536_CMD(x) (((x) & 0x7) << 5) +#define Z8536_CMD_NULL Z8536_CMD(0) /* Null Code */ +#define Z8536_CMD_CLR_IP_IUS Z8536_CMD(1) /* Clear IP & IUS */ +#define Z8536_CMD_SET_IUS Z8536_CMD(2) /* Set IUS */ +#define Z8536_CMD_CLR_IUS Z8536_CMD(3) /* Clear IUS */ +#define Z8536_CMD_SET_IP Z8536_CMD(4) /* Set IP */ +#define Z8536_CMD_CLR_IP Z8536_CMD(5) /* Clear IP */ +#define Z8536_CMD_SET_IE Z8536_CMD(6) /* Set IE */ +#define Z8536_CMD_CLR_IE Z8536_CMD(7) /* Clear IE */ +#define Z8536_CMD_MASK Z8536_CMD(7) #define Z8536_STAT_IUS BIT(7) /* Interrupt Under Service */ #define Z8536_STAT_IE BIT(6) /* Interrupt Enable */ @@ -105,46 +107,51 @@ #define Z8536_CT_MODE_ETE BIT(4) /* External Trigger Enable */ #define Z8536_CT_MODE_EGE BIT(3) /* External Gate Enable */ #define Z8536_CT_MODE_REB BIT(2) /* Retrigger Enable Bit */ -#define Z8536_CT_MODE_DCS_PULSE (0 << 0)/* Duty Cycle - Pulse */ -#define Z8536_CT_MODE_DCS_ONESHOT (1 << 0)/* Duty Cycle - One-Shot */ -#define Z8536_CT_MODE_DCS_SQRWAVE (2 << 0)/* Duty Cycle - Square Wave */ -#define Z8536_CT_MODE_DCS_DO_NOT_USE (3 << 0)/* Duty Cycle - Do Not Use */ -#define Z8536_CT_MODE_DCS_MASK (3 << 0)/* Duty Cycle mask */ +#define Z8536_CT_MODE_DCS(x) (((x) & 0x3) << 0) /* Duty Cycle */ +#define Z8536_CT_MODE_DCS_PULSE Z8536_CT_MODE_DCS(0) /* Pulse */ +#define Z8536_CT_MODE_DCS_ONESHOT Z8536_CT_MODE_DCS(1) /* One-Shot */ +#define Z8536_CT_MODE_DCS_SQRWAVE Z8536_CT_MODE_DCS(2) /* Square Wave */ +#define Z8536_CT_MODE_DCS_DO_NOT_USE Z8536_CT_MODE_DCS(3) /* Do Not Use */ +#define Z8536_CT_MODE_DCS_MASK Z8536_CT_MODE_DCS(3) /* Port A/B Mode Specification registers */ #define Z8536_PA_MODE_REG 0x20 #define Z8536_PB_MODE_REG 0x28 -#define Z8536_PAB_MODE_PTS_BIT (0 << 6)/* Bit Port */ -#define Z8536_PAB_MODE_PTS_INPUT (1 << 6)/* Input Port */ -#define Z8536_PAB_MODE_PTS_OUTPUT (2 << 6)/* Output Port */ -#define Z8536_PAB_MODE_PTS_BIDIR (3 << 6)/* Bidirectional Port */ -#define Z8536_PAB_MODE_PTS_MASK (3 << 6)/* Port Type Select mask */ +#define Z8536_PAB_MODE_PTS(x) (((x) & 0x3) << 6) /* Port type */ +#define Z8536_PAB_MODE_PTS_BIT Z8536_PAB_MODE_PTS(0 << 6)/* Bit */ +#define Z8536_PAB_MODE_PTS_INPUT Z8536_PAB_MODE_PTS(1 << 6)/* Input */ +#define Z8536_PAB_MODE_PTS_OUTPUT Z8536_PAB_MODE_PTS(2 << 6)/* Output */ +#define Z8536_PAB_MODE_PTS_BIDIR Z8536_PAB_MODE_PTS(3 << 6)/* Bidir */ +#define Z8536_PAB_MODE_PTS_MASK Z8536_PAB_MODE_PTS(3 << 6) #define Z8536_PAB_MODE_ITB BIT(5) /* Interrupt on Two Bytes */ #define Z8536_PAB_MODE_SB BIT(4) /* Single Buffered mode */ #define Z8536_PAB_MODE_IMO BIT(3) /* Interrupt on Match Only */ -#define Z8536_PAB_MODE_PMS_DISABLE (0 << 1)/* Disable Pattern Match */ -#define Z8536_PAB_MODE_PMS_AND (1 << 1)/* "AND" mode */ -#define Z8536_PAB_MODE_PMS_OR (2 << 1)/* "OR" mode */ -#define Z8536_PAB_MODE_PMS_OR_PEV (3 << 1)/* "OR-Priority" mode */ -#define Z8536_PAB_MODE_PMS_MASK (3 << 1)/* Pattern Mode mask */ +#define Z8536_PAB_MODE_PMS(x) (((x) & 0x3) << 1) /* Pattern Mode */ +#define Z8536_PAB_MODE_PMS_DISABLE Z8536_PAB_MODE_PMS(0)/* Disabled */ +#define Z8536_PAB_MODE_PMS_AND Z8536_PAB_MODE_PMS(1)/* "AND" */ +#define Z8536_PAB_MODE_PMS_OR Z8536_PAB_MODE_PMS(2)/* "OR" */ +#define Z8536_PAB_MODE_PMS_OR_PEV Z8536_PAB_MODE_PMS(3)/* "OR-Priority" */ +#define Z8536_PAB_MODE_PMS_MASK Z8536_PAB_MODE_PMS(3) #define Z8536_PAB_MODE_LPM BIT(0) /* Latch on Pattern Match */ #define Z8536_PAB_MODE_DTE BIT(0) /* Deskew Timer Enabled */ /* Port A/B Handshake Specification registers */ #define Z8536_PA_HANDSHAKE_REG 0x21 #define Z8536_PB_HANDSHAKE_REG 0x29 -#define Z8536_PAB_HANDSHAKE_HST_INTER (0 << 6)/* Interlocked Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_STROBED (1 << 6)/* Strobed Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_PULSED (2 << 6)/* Pulsed Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_3WIRE (3 << 6)/* Three-Wire Handshake */ -#define Z8536_PAB_HANDSHAKE_HST_MASK (3 << 6)/* Handshake Type mask */ -#define Z8536_PAB_HANDSHAKE_RWS_DISABLE (0 << 3)/* Req/Wait Disabled */ -#define Z8536_PAB_HANDSHAKE_RWS_OUTWAIT (1 << 3)/* Output Wait */ -#define Z8536_PAB_HANDSHAKE_RWS_INWAIT (3 << 3)/* Input Wait */ -#define Z8536_PAB_HANDSHAKE_RWS_SPREQ (4 << 3)/* Special Request */ -#define Z8536_PAB_HANDSHAKE_RWS_OUTREQ (5 << 4)/* Output Request */ -#define Z8536_PAB_HANDSHAKE_RWS_INREQ (7 << 3)/* Input Request */ -#define Z8536_PAB_HANDSHAKE_RWS_MASK (7 << 3)/* Req/Wait mask */ +#define Z8536_PAB_HANDSHAKE_HST(x) (((x) & 0x3) << 6) /* Handshake Type */ +#define Z8536_PAB_HANDSHAKE_HST_INTER Z8536_PAB_HANDSHAKE_HST(0)/*Interlock*/ +#define Z8536_PAB_HANDSHAKE_HST_STROBED Z8536_PAB_HANDSHAKE_HST(1)/* Strobed */ +#define Z8536_PAB_HANDSHAKE_HST_PULSED Z8536_PAB_HANDSHAKE_HST(2)/* Pulsed */ +#define Z8536_PAB_HANDSHAKE_HST_3WIRE Z8536_PAB_HANDSHAKE_HST(3)/* 3-Wire */ +#define Z8536_PAB_HANDSHAKE_HST_MASK Z8536_PAB_HANDSHAKE_HST(3) +#define Z8536_PAB_HANDSHAKE_RWS(x) (((x) & 0x7) << 3) /* Req/Wait */ +#define Z8536_PAB_HANDSHAKE_RWS_DISABLE Z8536_PAB_HANDSHAKE_RWS(0)/* Disabled */ +#define Z8536_PAB_HANDSHAKE_RWS_OUTWAIT Z8536_PAB_HANDSHAKE_RWS(1)/* Out Wait */ +#define Z8536_PAB_HANDSHAKE_RWS_INWAIT Z8536_PAB_HANDSHAKE_RWS(3)/* In Wait */ +#define Z8536_PAB_HANDSHAKE_RWS_SPREQ Z8536_PAB_HANDSHAKE_RWS(4)/* Special */ +#define Z8536_PAB_HANDSHAKE_RWS_OUTREQ Z8536_PAB_HANDSHAKE_RWS(5)/* Out Req */ +#define Z8536_PAB_HANDSHAKE_RWS_INREQ Z8536_PAB_HANDSHAKE_RWS(7)/* In Req */ +#define Z8536_PAB_HANDSHAKE_RWS_MASK Z8536_PAB_HANDSHAKE_RWS(7) #define Z8536_PAB_HANDSHAKE_DESKEW(x) ((x) << 0)/* Deskew Time */ #define Z8536_PAB_HANDSHAKE_DESKEW_MASK (3 << 0)/* Deskew Time mask */ -- 2.6.3 _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
