On Thursday, November 05, 2015 6:17 AM, Ian Abbott wrote:
> On 04/11/15 16:55, H Hartley Sweeten wrote:
>> Counters 1 and 2 of the 8254 are cascaeded to create the 32-bit timer
>> used for the analog input pacer trigger. The base clock to these counters
>> is 10 MHz.
>>
>> Counter 0 is available to the user for general purpose use. This counter
>> can use either an internal 1 MHz clock or an external clock. The
>> (*insn_config) for the counter subdevice provides support for
>> INSN_CONFIG_{SET,GET}_CLOCK_SRC to allow the user to select the
>> clock source to use. Fix the INSN_CONFIG_GET_CLOCK_SRC so it returns
>> the correct speed of the internal clock.
>>
>> Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx>
>> Cc: Ian Abbott <abbotti@xxxxxxxxx>
>> Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
>> ---
>> drivers/staging/comedi/drivers/adv_pci1710.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/staging/comedi/drivers/adv_pci1710.c b/drivers/staging/comedi/drivers/adv_pci1710.c
>> index c5f8bff..9e45f3d 100644
>> --- a/drivers/staging/comedi/drivers/adv_pci1710.c
>> +++ b/drivers/staging/comedi/drivers/adv_pci1710.c
>> @@ -701,7 +701,7 @@ static int pci1710_counter_insn_config(struct comedi_device *dev,
>> data[2] = 0;
>> } else {
>> data[1] = 0;
>> - data[2] = I8254_OSC_BASE_10MHZ;
>> + data[2] = I8254_OSC_BASE_1MHZ;
>> }
>> break;
>> default:
>>
>
> The manual I have says it's 1 MHz for PCI-1711/1711L/1716/1716L,
> and 100 kHz for PCI-1710/1710L/1710HG/1710HGL.
The data I have is a bit different.
The PCI-1710/1710HG User's manual I have has some issues....
The Specifications say:
Channel 1: 10 MHz
Channel 2: Takes input from output of channel 1
Channel 0: Internal 1 MHz or external clock (10 MHz max)
The Block Diagram also show a 1 MHz internal clock (10 MHz / 10) or
an external clock (CNT0_CLK pin).
The I/O connector description says this about the CNT0_CLK pin.
"Counter 0 Clock Input. This pin is the external clock input of counter 0.
The clock input of counter 0 can be either external (up to 10 MHz) or
Internal (100 kHz), as set up software."
The Trigger Source Connections says that all three counters are connected
to a 1 MHz clock.
The Control Register description says that:
"CNT0 Counter 0 clock source select bit
0 means that the clock source of Counter 0 comes from the internal clock
(100 kHz), and 1 means that the clock source of Counter 0 comes from the
external clock (maximum up to 10 MHz)."
The "A.1 The Intel 82C54" appendix says:
"The 82C54 has a maximum input clock frequency of 1 MHz. The PCI-1710/
1710HG provides 1 MHz input frequencies to the counter chip from an
on-board oscillator."
The PCI-1711/1731 manual I have is a bit better. The block diagram, I/O
Connector and CNT0 description all have a 1 MHz internal clock.
I think the manuals are a bit messed up. The 82C54 datasheet says that the
Chip can handle clock inputs up to 10 MHz. A 10 MHz base clock to the cascaded
counters is pretty typical for DAQ cards and a 1 MHz clock to the user counter
seems a bit more useful than a 100 kHz clock.
Hartley
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