[PATCH v2 17/17] staging: comedi: quatech_daqp_cs: tidy up register map defines

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Reorder the register map defines so that each register define is
followed by its bit defines.

For aesthetics, change all the register offsets to hex values and
use the BIT macro to define the register bits.

Also for aesthetics, move the DAQP_FIFO_SIZE and private data
definition after the register defines.

Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx>
Cc: Ian Abbott <abbotti@xxxxxxxxx>
Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
 drivers/staging/comedi/drivers/quatech_daqp_cs.c | 172 ++++++++++++-----------
 1 file changed, 92 insertions(+), 80 deletions(-)

diff --git a/drivers/staging/comedi/drivers/quatech_daqp_cs.c b/drivers/staging/comedi/drivers/quatech_daqp_cs.c
index 3c1ba5c..0d39c89 100644
--- a/drivers/staging/comedi/drivers/quatech_daqp_cs.c
+++ b/drivers/staging/comedi/drivers/quatech_daqp_cs.c
@@ -42,96 +42,108 @@
 
 #include "../comedi_pcmcia.h"
 
-struct daqp_private {
-	unsigned int pacer_div;
-	unsigned char scanrate;
-	int stop;
-};
+/*
+ * Register I/O map
+ *
+ * The D/A and timer registers can be accessed with 16-bit or 8-bit I/O
+ * instructions. All other registers can only use 8-bit instructions.
+ *
+ * The FIFO and scanlist registers require two 8-bit instructions to
+ * access the 16-bit data. Data is transferred LSB then MSB.
+ */
+#define DAQP_FIFO			0x00
 
-/* The DAQP communicates with the system through a 16 byte I/O window. */
-
-#define DAQP_FIFO_SIZE		4096
-
-#define DAQP_FIFO		0
-#define DAQP_SCANLIST		1
-#define DAQP_CONTROL		2
-#define DAQP_STATUS		2
-#define DAQP_DIGITAL_IO		3
-#define DAQP_PACER_LOW		4
-#define DAQP_PACER_MID		5
-#define DAQP_PACER_HIGH		6
-#define DAQP_COMMAND		7
-#define DAQP_DA			8
-#define DAQP_TIMER		10
-#define DAQP_AUX		15
-
-#define DAQP_SCANLIST_DIFFERENTIAL	0x4000
-#define DAQP_SCANLIST_GAIN(x)		((x) << 12)
-#define DAQP_SCANLIST_CHANNEL(x)	((x) << 8)
-#define DAQP_SCANLIST_START		0x0080
-#define DAQP_SCANLIST_EXT_GAIN(x)	((x) << 4)
-#define DAQP_SCANLIST_EXT_CHANNEL(x)	(x)
+#define DAQP_SCANLIST			0x01
+#define DAQP_SCANLIST_DIFFERENTIAL	BIT(14)
+#define DAQP_SCANLIST_GAIN(x)		(((x) & 0x3) << 12)
+#define DAQP_SCANLIST_CHANNEL(x)	(((x) & 0xf) << 8)
+#define DAQP_SCANLIST_START		BIT(7)
+#define DAQP_SCANLIST_EXT_GAIN(x)	(((x) & 0x3) << 4)
+#define DAQP_SCANLIST_EXT_CHANNEL(x)	(((x) & 0xf) << 0)
 
+#define DAQP_CONTROL			0x02
 #define DAQP_CONTROL_PACER_CLK(x)	(((x) & 0x3) << 6)
 #define DAQP_CONTROL_PACER_CLK_EXT	DAQP_CONTROL_PACER_CLK(0)
 #define DAQP_CONTROL_PACER_CLK_5MHZ	DAQP_CONTROL_PACER_CLK(1)
 #define DAQP_CONTROL_PACER_CLK_1MHZ	DAQP_CONTROL_PACER_CLK(2)
 #define DAQP_CONTROL_PACER_CLK_100KHZ	DAQP_CONTROL_PACER_CLK(3)
-#define DAQP_CONTORL_EXPANSION		0x20
-#define DAQP_CONTROL_EOS_INT_ENABLE	0x10
-#define DAQP_CONTROL_FIFO_INT_ENABLE	0x08
-#define DAQP_CONTROL_TRIGGER_ONESHOT	0x00
-#define DAQP_CONTROL_TRIGGER_CONTINUOUS	0x04
-#define DAQP_CONTROL_TRIGGER_INTERNAL	0x00
-#define DAQP_CONTROL_TRIGGER_EXTERNAL	0x02
-#define DAQP_CONTROL_TRIGGER_RISING	0x00
-#define DAQP_CONTROL_TRIGGER_FALLING	0x01
-
-#define DAQP_STATUS_IDLE		0x80
-#define DAQP_STATUS_RUNNING		0x40
-#define DAQP_STATUS_EVENTS		0x38
-#define DAQP_STATUS_DATA_LOST		0x20
-#define DAQP_STATUS_END_OF_SCAN		0x10
-#define DAQP_STATUS_FIFO_THRESHOLD	0x08
-#define DAQP_STATUS_FIFO_FULL		0x04
-#define DAQP_STATUS_FIFO_NEARFULL	0x02
-#define DAQP_STATUS_FIFO_EMPTY		0x01
-
-#define DAQP_COMMAND_ARM		0x80
-#define DAQP_COMMAND_RSTF		0x40
-#define DAQP_COMMAND_RSTQ		0x20
-#define DAQP_COMMAND_STOP		0x10
-#define DAQP_COMMAND_LATCH		0x08
+#define DAQP_CONTORL_EXPANSION		BIT(5)
+#define DAQP_CONTROL_EOS_INT_ENABLE	BIT(4)
+#define DAQP_CONTROL_FIFO_INT_ENABLE	BIT(3)
+#define DAQP_CONTROL_TRIGGER_MODE	BIT(2)	/* 0=one-shot; 1=continuous */
+#define DAQP_CONTROL_TRIGGER_SRC	BIT(1)	/* 0=internal; 1=external */
+#define DAQP_CONTROL_TRIGGER_EDGE	BIT(0)	/* 0=rising; 1=falling */
+
+#define DAQP_STATUS			0x02
+#define DAQP_STATUS_IDLE		BIT(7)
+#define DAQP_STATUS_RUNNING		BIT(6)
+#define DAQP_STATUS_DATA_LOST		BIT(5)
+#define DAQP_STATUS_END_OF_SCAN		BIT(4)
+#define DAQP_STATUS_FIFO_THRESHOLD	BIT(3)
+#define DAQP_STATUS_FIFO_FULL		BIT(2)
+#define DAQP_STATUS_FIFO_NEARFULL	BIT(1)
+#define DAQP_STATUS_FIFO_EMPTY		BIT(0)
+/* these bits clear when the Status register is read */
+#define DAQP_STATUS_EVENTS		(DAQP_STATUS_DATA_LOST |	\
+					 DAQP_STATUS_END_OF_SCAN |	\
+					 DAQP_STATUS_FIFO_THRESHOLD)
+
+#define DAQP_DIGITAL_IO			0x03
+
+#define DAQP_PACER_LOW			0x04
+#define DAQP_PACER_MID			0x05
+#define DAQP_PACER_HIGH			0x06
+
+#define DAQP_COMMAND			0x07
+/* the monostable bits are self-clearing after the function is complete */
+#define DAQP_COMMAND_ARM		BIT(7)	/* monostable */
+#define DAQP_COMMAND_RSTF		BIT(6)	/* monostable */
+#define DAQP_COMMAND_RSTQ		BIT(5)	/* monostable */
+#define DAQP_COMMAND_STOP		BIT(4)	/* monostable */
+#define DAQP_COMMAND_LATCH		BIT(3)	/* monostable */
 #define DAQP_COMMAND_SCANRATE(x)	(((x) & 0x3) << 1)
 #define DAQP_COMMAND_SCANRATE_100KHZ	DAQP_COMMAND_SCANRATE(0)
 #define DAQP_COMMAND_SCANRATE_50KHZ	DAQP_COMMAND_SCANRATE(1)
 #define DAQP_COMMAND_SCANRATE_25KHZ	DAQP_COMMAND_SCANRATE(2)
-#define DAQP_COMMAND_FIFO_DATA		0x01
-#define DAQP_COMMAND_FIFO_PROGRAM	0x00
-
-#define DAQP_AUX_TRIGGER_TTL		0x00
-#define DAQP_AUX_TRIGGER_ANALOG		0x80
-#define DAQP_AUX_TRIGGER_PRETRIGGER	0x40
-#define DAQP_AUX_TIMER_INT_ENABLE	0x20
-#define DAQP_AUX_TIMER_RELOAD		0x00
-#define DAQP_AUX_TIMER_PAUSE		0x08
-#define DAQP_AUX_TIMER_GO		0x10
-#define DAQP_AUX_TIMER_GO_EXTERNAL	0x18
-#define DAQP_AUX_TIMER_EXTERNAL_SRC	0x04
-#define DAQP_AUX_TIMER_INTERNAL_SRC	0x00
-#define DAQP_AUX_DA_DIRECT		0x00
-#define DAQP_AUX_DA_OVERFLOW		0x01
-#define DAQP_AUX_DA_EXTERNAL		0x02
-#define DAQP_AUX_DA_PACER		0x03
-
-#define DAQP_AUX_RUNNING		0x80
-#define DAQP_AUX_TRIGGERED		0x40
-#define DAQP_AUX_DA_BUFFER		0x20
-#define DAQP_AUX_TIMER_OVERFLOW		0x10
-#define DAQP_AUX_CONVERSION		0x08
-#define DAQP_AUX_DATA_LOST		0x04
-#define DAQP_AUX_FIFO_NEARFULL		0x02
-#define DAQP_AUX_FIFO_EMPTY		0x01
+#define DAQP_COMMAND_FIFO_DATA		BIT(0)
+
+#define DAQP_DA				0x08	/* and 0x09 (16-bit) */
+
+#define DAQP_TIMER			0x0a	/* and 0x0b (16-bit) */
+
+#define DAQP_AUX			0x0f
+/* Auxiliary Control register bits */
+#define DAQP_AUX_EXT_ANALOG_TRIGGER	BIT(7)
+#define DAQP_AUX_PRETRIGGER		BIT(6)
+#define DAQP_AUX_TIMER_INT_ENABLE	BIT(5)
+#define DAQP_AUX_TIMER_MODE(x)		(((x) & 0x3) << 3)
+#define DAQP_AUX_TIMER_MODE_RELOAD	DAQP_AUX_TIMER_MODE(0)
+#define DAQP_AUX_TIMER_MODE_PAUSE	DAQP_AUX_TIMER_MODE(1)
+#define DAQP_AUX_TIMER_MODE_GO		DAQP_AUX_TIMER_MODE(2)
+#define DAQP_AUX_TIMER_MODE_EXTERNAL	DAQP_AUX_TIMER_MODE(3)
+#define DAQP_AUX_TIMER_CLK_SRC_EXT	BIT(2)
+#define DAQP_AUX_DA_UPDATE(x)		(((x) & 0x3) << 0)
+#define DAQP_AUX_DA_UPDATE_DIRECT	DAQP_AUX_DA_UPDATE(0)
+#define DAQP_AUX_DA_UPDATE_OVERFLOW	DAQP_AUX_DA_UPDATE(1)
+#define DAQP_AUX_DA_UPDATE_EXTERNAL	DAQP_AUX_DA_UPDATE(2)
+#define DAQP_AUX_DA_UPDATE_PACER	DAQP_AUX_DA_UPDATE(3)
+/* Auxiliary Status register bits */
+#define DAQP_AUX_RUNNING		BIT(7)
+#define DAQP_AUX_TRIGGERED		BIT(6)
+#define DAQP_AUX_DA_BUFFER		BIT(5)
+#define DAQP_AUX_TIMER_OVERFLOW		BIT(4)
+#define DAQP_AUX_CONVERSION		BIT(3)
+#define DAQP_AUX_DATA_LOST		BIT(2)
+#define DAQP_AUX_FIFO_NEARFULL		BIT(1)
+#define DAQP_AUX_FIFO_EMPTY		BIT(0)
+
+#define DAQP_FIFO_SIZE			4096	/* in bytes */
+
+struct daqp_private {
+	unsigned int pacer_div;
+	unsigned char scanrate;
+	int stop;
+};
 
 static const struct comedi_lrange range_daqp_ai = {
 	4, {
@@ -550,7 +562,7 @@ static int daqp_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 
 	/* 5 MHz pacer, FIFO threshold interrupt, continuous internal trigger */
 	outb(DAQP_CONTROL_PACER_CLK_5MHZ | DAQP_CONTROL_FIFO_INT_ENABLE |
-	     DAQP_CONTROL_TRIGGER_CONTINUOUS | DAQP_CONTROL_TRIGGER_INTERNAL,
+	     DAQP_CONTROL_TRIGGER_MODE,
 	     dev->iobase + DAQP_CONTROL);
 
 	ret = daqp_clear_events(dev, 100);
-- 
2.5.1

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