Hi Alan, On Fri, Aug 14, 2015 at 8:46 AM, atull <atull@xxxxxxxxxxxxxxxxxxxxx> wrote: > On Fri, 14 Aug 2015, atull wrote: > >> On Fri, 14 Aug 2015, Moritz Fischer wrote: >> >> > Hi Alan, >> > >> > I've updated my Zynq driver (it can be found in an older version >> > against your v8 in the Xilinx tree, too) >> > >> > https://github.com/mfischer/linux/tree/alan-fpga-mgr-v10 >> >> Since we are both already using this and have been for a while now, I hope it >> can go up into the mainstream instead of continuing to exist only in Altera >> and Xilinx's git trees. Yeah, that was definitely my intention. I just held off submitting my driver for mainline, because your patchset was still sort of a moving target. And that would be like the 3rd layer of dependencies :-) The reason for inclusion into the Xilinx tree was so people can play around with it already. >> > > Hi Moritz, > > I fetched your git tree and took a look at your low level driver. > > I had a some feedback. write_complete() is a blocking call, waiting for the > FPGA to go into operating state and timing out (ETIMEDOUT) if necessary. The > fpga-mgr.c framework is assuming that when write_complete exits with status 0, > that means that the FPGA is in operating state. That's why it's proper for us > to add "mgr->state = FPGA_MGR_STATE_OPERATING" after write_complete returns > success as you noted. My suggestion is that your write_complete() should check > status in this way. Whatever error codes it returns will get propagated. Fair enough, I had misunderstood the API then :-) Another option would have been to have the sysfs function actually query the state function instead of using the cached mgr->state value. I'll fix my driver ;-) I'll probably do something like #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \ readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \ timeout_us) > > Also, I'm wondering how the simple-fpga-bus stuff looks to you now that you've > had it for a little while. To be honest I haven't played much with it aside from making sure it works. I had to submit another patchset for the Zynq's reset controller to make it work. The whole dt overlay is pretty cool, but the syntax took some getting used to. > > Thank, > Alan Thanks for your feedback, Moritz _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
