Rename the CamelCase. The bit defines are identical to NISTC_INTA_ENA_REG.
Reuse them.
Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx>
Cc: Ian Abbott <abbotti@xxxxxxxxx>
Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/staging/comedi/drivers/ni_mio_common.c | 6 +++---
drivers/staging/comedi/drivers/ni_stc.h | 15 +--------------
2 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c
index 0651aed..0e7075d 100644
--- a/drivers/staging/comedi/drivers/ni_mio_common.c
+++ b/drivers/staging/comedi/drivers/ni_mio_common.c
@@ -367,7 +367,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
[NISTC_AO_MODE3_REG] = { 0x18c, 2 },
[NISTC_RESET_REG] = { 0x190, 2 },
[NISTC_INTA_ENA_REG] = { 0x192, 2 },
- [Second_IRQ_A_Enable_Register] = { 0, 0 }, /* E-Series only */
+ [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
[Interrupt_B_Enable_Register] = { 0x196, 2 },
[Second_IRQ_B_Enable_Register] = { 0, 0 }, /* E-Series only */
[AI_Personal_Register] = { 0x19a, 2 },
@@ -818,9 +818,9 @@ static void ni_e_series_enable_second_irq(struct comedi_device *dev,
* dma requests for their counters
*/
if (gpct_index == 0) {
- reg = Second_IRQ_A_Enable_Register;
+ reg = NISTC_INTA2_ENA_REG;
if (enable)
- val = G0_Gate_Second_Irq_Enable;
+ val = NISTC_INTA_ENA_G0_GATE;
} else {
reg = Second_IRQ_B_Enable_Register;
if (enable)
diff --git a/drivers/staging/comedi/drivers/ni_stc.h b/drivers/staging/comedi/drivers/ni_stc.h
index 81a918e..6f6c821 100644
--- a/drivers/staging/comedi/drivers/ni_stc.h
+++ b/drivers/staging/comedi/drivers/ni_stc.h
@@ -385,6 +385,7 @@
#define NISTC_RESET_AI BIT(0)
#define NISTC_INTA_ENA_REG 73
+#define NISTC_INTA2_ENA_REG 74
#define NISTC_INTA_ENA_PASSTHRU0 BIT(9)
#define NISTC_INTA_ENA_G0_GATE BIT(8)
#define NISTC_INTA_ENA_AI_FIFO BIT(7)
@@ -475,20 +476,6 @@ enum Joint_Status_2_Bits {
#define AO_START1_Interrupt_Enable _bit1
#define AO_BC_TC_Interrupt_Enable _bit0
-#define Second_IRQ_A_Enable_Register 74
-enum Second_IRQ_A_Enable_Bits {
- AI_SC_TC_Second_Irq_Enable = _bit0,
- AI_START1_Second_Irq_Enable = _bit1,
- AI_START2_Second_Irq_Enable = _bit2,
- AI_START_Second_Irq_Enable = _bit3,
- AI_STOP_Second_Irq_Enable = _bit4,
- AI_Error_Second_Irq_Enable = _bit5,
- G0_TC_Second_Irq_Enable = _bit6,
- AI_FIFO_Second_Irq_Enable = _bit7,
- G0_Gate_Second_Irq_Enable = _bit8,
- Pass_Thru_0_Second_Irq_Enable = _bit9
-};
-
#define Second_IRQ_B_Enable_Register 76
enum Second_IRQ_B_Enable_Bits {
AO_BC_TC_Second_Irq_Enable = _bit0,
--
2.3.0
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