[PATCH 2/2] setting sig_cfg.clk_pol according to value of pixelclk-active

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Signed-off-by: stefan <strawberryblack@xxxxxxxxxxxxxx>
---
 drivers/staging/imx-drm/ipuv3-crtc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 720868b..71c741b 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -166,7 +166,9 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 		sig_cfg.Vsync_pol = 1;
 
 	sig_cfg.enable_pol = 1;
-	sig_cfg.clk_pol = 0;
+	sig_cfg.clk_pol = 0; /* rising edge */
+	if (mode->private_flags & DRM_MODE_FLAG_PCSYNC) /* falling edge  */
+		sig_cfg.clk_pol = 1;
 	sig_cfg.width = mode->hdisplay;
 	sig_cfg.height = mode->vdisplay;
 	sig_cfg.pixel_fmt = out_pixel_fmt;
-- 
2.1.1

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