On Mon, Jun 09, 2014 at 03:38:55PM -0300, Fabio Estevam wrote:
> On Mon, Jun 9, 2014 at 3:15 PM, Fabio Estevam <festevam@xxxxxxxxx> wrote:
> >> I wonder if the problem is that HDMI and LVDS are interfering with each
> >> other wrt the required pixel clock, and LVDS is winning. If we have
> >> HDMI enabled, many HDMI sinks will only work if we set one of their
> >> supported modes (with the dot clock within 1% - though some sinks are
> >> more lenient).
> >
> > Yes, it seems this is the case.
>
> I tested not using pll5 as the parent of LVDS:
>
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -439,12 +439,6 @@ static void __init imx6q_clocks_init(struct device_node *cc
> clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
> clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
>
> - if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
> - cpu_is_imx6dl()) {
> - clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
> - clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
> - }
> -
> clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
> clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
> clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
>
>
> Then the HDMI detection works fine and I get images on both HDMI and LVDS.
>
> I understand that many LVDS panels need a frequency range that can
> only be obtained via PLL5 though.
HDMI pretty much fundamentally requires PLL5.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
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