On Monday, January 20, 2014 11:06 AM, Greg KH wrote: > On Mon, Jan 20, 2014 at 09:16:08AM -0800, Insop Song wrote: >> On Thu, Jan 16, 2014 at 1:41 PM, Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> wrote: >>> On Thu, Jan 16, 2014 at 11:47:41AM -0800, Insop Song wrote: >>>>>> There is no way to detect FPGA until it is programmed. >>>>>> This is a reason and the only reason of this driver to download the >>>>>> program to the FPGA so that it can function. >>>>> >>>>> So how do you get the memory locations of where the FPGA is in the >>>>> system in order to be able to send data to it? Surely that's in the >>>>> device tree file somewhere, right? >>>>> >>>> >>>> On the FPGA side, there are dedicated pins for programming, and >>>> through these you cannot get meaningful information (again unless you >>>> are JTAG capable) >>>> Such as these on the FPGA side, PROGRAM_B, INIT_B, CCLK, D[0:7], and DONE. >>>> On a process side, we use gpio pin to connect to the above pins. >>>> It's GPIO pins that we do the bit banging as defined for programming >>>> guide from Xilinx. >>> >>> Yes, but where do you learn about how those pins are hooked up to the >>> CPU so that the driver can control them? >>> >> This is hard coded. > > Really? Shouldn't they be in a board file or device tree attribute > somewhere? What happens in the next board that is created with this > chip and the memory locations are in a different place? I have not looked at this driver but... Couldn't this be done from user space using urjtag? http://urjtag.org/ Regards, Hartley _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
