[PATCH v2 2/2] stagin: fpgaboot: Driver for downloading Xilinx FPGA image

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Review feedback, add TODO, remove EXPORT_SYMBOL, update README fie format

Signed-off-by: Insop Song <insop.song@xxxxxxxxxxxxx>
---
 drivers/staging/gs_fpgaboot/README        |   50 +++++++++++------------------
 drivers/staging/gs_fpgaboot/TODO          |   14 ++++++++
 drivers/staging/gs_fpgaboot/gs_fpgaboot.c |    1 -
 drivers/staging/gs_fpgaboot/io.c          |   17 +---------
 4 files changed, 33 insertions(+), 49 deletions(-)
 create mode 100644 drivers/staging/gs_fpgaboot/TODO

diff --git a/drivers/staging/gs_fpgaboot/README b/drivers/staging/gs_fpgaboot/README
index 0f301a0..834100b 100644
--- a/drivers/staging/gs_fpgaboot/README
+++ b/drivers/staging/gs_fpgaboot/README
@@ -1,8 +1,5 @@
 ==============================================================================
 Linux Driver Source for Xilinx FPGA image download
-
-* Gainspeed, Inc.
-* Insop Song <INSOP dot SONG at GAINSPEED dot COM>
 ==============================================================================
 
 
@@ -14,47 +11,36 @@ TABLE OF CONTENTS.
 4.  HOW TO USE
 5.  REFERENCE
 
-------------------------------------------------------------------------------
 1. SUMMARY
-------------------------------------------------------------------------------
 
-	* Download Xilinx FPGA image
-	* This module downloads Xilinx FPGA image using gpio pins.
+	- Download Xilinx FPGA image
+	- This module downloads Xilinx FPGA image using gpio pins.
 
-------------------------------------------------------------------------------
 2. BACKGROUND
-------------------------------------------------------------------------------
-
-An FPGA (Field Programmable Gate Array) is a programmable hardware that is
-used in various applications. Hardware design needs to programmed through
-a dedicated device or CPU assisted way (serial or parallel).
-
-This driver provides a way to download FPGA image.
 
+	An FPGA (Field Programmable Gate Array) is a programmable hardware that is
+	used in various applications. Hardware design needs to programmed through
+	a dedicated device or CPU assisted way (serial or parallel).
+	This driver provides a way to download FPGA image.
 
-
-------------------------------------------------------------------------------
 3. DESIGN
-------------------------------------------------------------------------------
-* load Xilinx FPGA bitstream format[1] image using kernel firmware framework,
-request_firmware()
-* program the Xilinx FPGA using SelectMAP (parallel) mode [2]
-* FPGA prgram is done by gpio based bit-banging, as an example
-* platform independent file: gs_fpgaboot.c
-* platform dependent file: io.c
+
+	- load Xilinx FPGA bitstream format[1] image using kernel firmware
+	  framework, request_firmware()
+	- program the Xilinx FPGA using SelectMAP (parallel) mode [2]
+	- FPGA prgram is done by gpio based bit-banging, as an example
+	- platform independent file: gs_fpgaboot.c
+	- platform dependent file: io.c
 	
 
-------------------------------------------------------------------------------
 4. HOW TO USE
-------------------------------------------------------------------------------
+
 	$ insmod gs_fpga.ko file="xlinx_fpga_top_bitstream.bit"
 	$ rmmod gs_fpga
 
-------------------------------------------------------------------------------
 5. REFERENCE
-------------------------------------------------------------------------------
 
-1. Xilinx APP NOTE XAPP583:
-http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
-2. bitstream file info:
-http://home.earthlink.net/~davesullins/software/bitinfo.html
+	1. Xilinx APP NOTE XAPP583:
+	  http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
+	2. bitstream file info:
+	  http://home.earthlink.net/~davesullins/software/bitinfo.html
diff --git a/drivers/staging/gs_fpgaboot/TODO b/drivers/staging/gs_fpgaboot/TODO
new file mode 100644
index 0000000..1e4299b
--- /dev/null
+++ b/drivers/staging/gs_fpgaboot/TODO
@@ -0,0 +1,14 @@
+TODO:
+        - get bus width input instead of hardcoded bus width
+
+	- make it easier to config different programming method for
+	  other embedded targets, such as, different combination of gpio
+	  or serial programming
+
+DONE:
+	- run checkpatch
+	- build tested
+
+Please send any patches for this driver to Insop Song<insop.song@xxxxxxxxx>
+and Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>. And please CC linux-usb
+<linux-usb@xxxxxxxxxxxxxxx> too.
diff --git a/drivers/staging/gs_fpgaboot/gs_fpgaboot.c b/drivers/staging/gs_fpgaboot/gs_fpgaboot.c
index 95952c4..b147585 100644
--- a/drivers/staging/gs_fpgaboot/gs_fpgaboot.c
+++ b/drivers/staging/gs_fpgaboot/gs_fpgaboot.c
@@ -7,7 +7,6 @@
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
diff --git a/drivers/staging/gs_fpgaboot/io.c b/drivers/staging/gs_fpgaboot/io.c
index 079e8a0..d145026 100644
--- a/drivers/staging/gs_fpgaboot/io.c
+++ b/drivers/staging/gs_fpgaboot/io.c
@@ -55,7 +55,6 @@ void xl_shift_cclk(int count)
 		xl_cclk_b(0);
 	}
 }
-EXPORT_SYMBOL(xl_shift_cclk);
 
 int xl_supported_prog_bus_width(enum wbus bus_bytes)
 {
@@ -72,7 +71,6 @@ int xl_supported_prog_bus_width(enum wbus bus_bytes)
 
 	return 1;
 }
-EXPORT_SYMBOL(xl_supported_prog_bus_width);
 
 /* Serialize byte and clock each bit on target's DIN and CCLK pins */
 void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata)
@@ -86,7 +84,6 @@ void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata)
 	byte1_out(pdata[1]);
 	xl_shift_cclk(1);
 }
-EXPORT_SYMBOL(xl_shift_bytes_out);
 
 /*
  * generic bit swap for xilinx SYSTEMMAP FPGA programming
@@ -167,31 +164,26 @@ void xl_program_b(int32_t i)
 {
 	gpio_set_value(XL_PROGN_PORT, XL_PROGN_PIN, i);
 }
-EXPORT_SYMBOL(xl_program_b);
 
 void xl_rdwr_b(int32_t i)
 {
 	gpio_set_value(XL_RDWRN_PORT, XL_RDWRN_PIN, i);
 }
-EXPORT_SYMBOL(xl_rdwr_b);
 
 void xl_csi_b(int32_t i)
 {
 	gpio_set_value(XL_CSIN_PORT, XL_CSIN_PIN, i);
 }
-EXPORT_SYMBOL(xl_csi_b);
 
 int xl_get_init_b(void)
 {
 	return gpio_get_value(XL_INITN_PORT, XL_INITN_PIN);
 }
-EXPORT_SYMBOL(xl_get_init_b);
 
 int xl_get_done_b(void)
 {
 	return gpio_get_value(XL_DONE_PORT, XL_DONE_PIN);
 }
-EXPORT_SYMBOL(xl_get_done_b);
 
 
 /* G100 specific bit swap and remmap (to gpio pins) for byte 0 */
@@ -225,7 +217,7 @@ static inline void byte1_out(unsigned char data)
 /*
  * TODO:
  * - configurable per device type for different I/O config
- * so that this can be easily extended to G200 and more
+ * so that this can be easily extended other target devices
  *
  * - have a device specific data struct (config, and func ptrs)
  *
@@ -260,7 +252,6 @@ int xl_init_io()
 
 	return 0;
 }
-EXPORT_SYMBOL(xl_init_io);
 
 
 #else	/* placeholder for boards with different config */
@@ -269,31 +260,26 @@ void xl_program_b(int32_t i)
 {
 	return;
 }
-EXPORT_SYMBOL(xl_program_b);
 
 void xl_rdwr_b(int32_t i)
 {
 	return;
 }
-EXPORT_SYMBOL(xl_rdwr_b);
 
 void xl_csi_b(int32_t i)
 {
 	return;
 }
-EXPORT_SYMBOL(xl_csi_b);
 
 int xl_get_init_b(void)
 {
 	return -1;
 }
-EXPORT_SYMBOL(xl_get_init_b);
 
 int xl_get_done_b(void)
 {
 	return -1;
 }
-EXPORT_SYMBOL(xl_get_done_b);
 
 
 /* G100 specific bit swap and remmap (to gpio pins) for byte 0 */
@@ -326,6 +312,5 @@ int xl_init_io()
 {
 	return -1;
 }
-EXPORT_SYMBOL(xl_init_io);
 
 #endif /* CONFIG_B4860G100 */
-- 
1.7.9.5

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