This module downloads Xilinx FPGA image using gpio pins DESIGN ------ * load Xilinx FPGA bitstream format[1] image using kernel firmware * framework, request_firmware() * program the Xilinx FPGA using SelectMAP (parallel) mode [2] * FPGA prgram is done by gpio based bit-banging, as an example * platform independent file: gs_fpgaboot.c * platform dependent file: io.c Signed-off-by: Insop Song <insop.song@xxxxxxxxxxxxx> --- drivers/staging/Kconfig | 2 + drivers/staging/Makefile | 1 + drivers/staging/gs_fpgaboot/Kconfig | 8 + drivers/staging/gs_fpgaboot/Makefile | 4 + drivers/staging/gs_fpgaboot/README | 60 ++++ drivers/staging/gs_fpgaboot/gs_fpgaboot.c | 505 +++++++++++++++++++++++++++++ drivers/staging/gs_fpgaboot/gs_fpgaboot.h | 56 ++++ drivers/staging/gs_fpgaboot/io.c | 331 +++++++++++++++++++ drivers/staging/gs_fpgaboot/io.h | 90 +++++ 9 files changed, 1057 insertions(+) create mode 100644 drivers/staging/gs_fpgaboot/Kconfig create mode 100644 drivers/staging/gs_fpgaboot/Makefile create mode 100644 drivers/staging/gs_fpgaboot/README create mode 100644 drivers/staging/gs_fpgaboot/gs_fpgaboot.c create mode 100644 drivers/staging/gs_fpgaboot/gs_fpgaboot.h create mode 100644 drivers/staging/gs_fpgaboot/io.c create mode 100644 drivers/staging/gs_fpgaboot/io.h diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index d2beb07..c5c1c9c 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -150,4 +150,6 @@ source "drivers/staging/dgnc/Kconfig" source "drivers/staging/dgap/Kconfig" +source "drivers/staging/gs_fpgaboot/Kconfig" + endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index bf62386..9359019 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -67,3 +67,4 @@ obj-$(CONFIG_XILLYBUS) += xillybus/ obj-$(CONFIG_DGNC) += dgnc/ obj-$(CONFIG_DGAP) += dgap/ obj-$(CONFIG_MTD_SPINAND_MT29F) += mt29f_spinand/ +obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/ diff --git a/drivers/staging/gs_fpgaboot/Kconfig b/drivers/staging/gs_fpgaboot/Kconfig new file mode 100644 index 0000000..4fbbae1 --- /dev/null +++ b/drivers/staging/gs_fpgaboot/Kconfig @@ -0,0 +1,8 @@ +# +# "xilinx fpga download, fpgaboot" +# +config GS_FPGABOOT + tristate "Xilinx FPGA bitstream image download" + default n + help + Xilinx FPGA program image download diff --git a/drivers/staging/gs_fpgaboot/Makefile b/drivers/staging/gs_fpgaboot/Makefile new file mode 100644 index 0000000..34cb606 --- /dev/null +++ b/drivers/staging/gs_fpgaboot/Makefile @@ -0,0 +1,4 @@ +gs_fpga-y += gs_fpgaboot.o io.o +obj-$(CONFIG_GS_FPGABOOT) += gs_fpga.o + +ccflags-$(CONFIG_GS_FPGA_DEBUG) := -DDEBUG diff --git a/drivers/staging/gs_fpgaboot/README b/drivers/staging/gs_fpgaboot/README new file mode 100644 index 0000000..0f301a0 --- /dev/null +++ b/drivers/staging/gs_fpgaboot/README @@ -0,0 +1,60 @@ +============================================================================== +Linux Driver Source for Xilinx FPGA image download + +* Gainspeed, Inc. +* Insop Song <INSOP dot SONG at GAINSPEED dot COM> +============================================================================== + + +TABLE OF CONTENTS. + +1. SUMMARY +2. BACKGROUND +3. DESIGN +4. HOW TO USE +5. REFERENCE + +------------------------------------------------------------------------------ +1. SUMMARY +------------------------------------------------------------------------------ + + * Download Xilinx FPGA image + * This module downloads Xilinx FPGA image using gpio pins. + +------------------------------------------------------------------------------ +2. BACKGROUND +------------------------------------------------------------------------------ + +An FPGA (Field Programmable Gate Array) is a programmable hardware that is +used in various applications. Hardware design needs to programmed through +a dedicated device or CPU assisted way (serial or parallel). + +This driver provides a way to download FPGA image. + + + +------------------------------------------------------------------------------ +3. DESIGN +------------------------------------------------------------------------------ +* load Xilinx FPGA bitstream format[1] image using kernel firmware framework, +request_firmware() +* program the Xilinx FPGA using SelectMAP (parallel) mode [2] +* FPGA prgram is done by gpio based bit-banging, as an example +* platform independent file: gs_fpgaboot.c +* platform dependent file: io.c + + +------------------------------------------------------------------------------ +4. HOW TO USE +------------------------------------------------------------------------------ + $ insmod gs_fpga.ko file="xlinx_fpga_top_bitstream.bit" + $ rmmod gs_fpga + +------------------------------------------------------------------------------ +5. REFERENCE +------------------------------------------------------------------------------ + +1. Xilinx APP NOTE XAPP583: +http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf +2. bitstream file info: +http://home.earthlink.net/~davesullins/software/bitinfo.html diff --git a/drivers/staging/gs_fpgaboot/gs_fpgaboot.c b/drivers/staging/gs_fpgaboot/gs_fpgaboot.c new file mode 100644 index 0000000..95952c4 --- /dev/null +++ b/drivers/staging/gs_fpgaboot/gs_fpgaboot.c @@ -0,0 +1,505 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/fs.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/delay.h> + +#include <include/asm/io.h> +#include <linux/firmware.h> + +#include "gs_fpgaboot.h" +#include "io.h" + +#define DEVICE_NAME "device" +#define CLASS_NAME "fpgaboot" + +static uint8_t bits_magic[] = { + 0x0, 0x9, 0xf, 0xf0, 0xf, 0xf0, + 0xf, 0xf0, 0xf, 0xf0, 0x0, 0x0, 0x1}; +/* + * Device variables + */ +static int fpga_major; +static struct class *fpga_class; +static struct device *fpga_device; + +static char *file = "xlinx_fpga_top_bitstream.bit"; +module_param(file, charp, S_IRUGO); +MODULE_PARM_DESC(file, "FPGA image file name."); + +#ifdef DEBUG_FPGA +static void datadump(char *msg, void *m, int n) +{ + int i; + unsigned char *c; + + pr_info("=== %s ===\n", msg); + + c = m; + + for (i = 0; i < n; i++) { + if ((i&0xf) == 0) + pr_info(KERN_INFO "\n 0x%4x: ", i); + + pr_info("%02X ", c[i]); + } + + pr_info("\n"); +} +#endif /* DEBUG_FPGA */ + +static void read_bitstream(char *bitdata, char *buf, int *offset, int rdsize) +{ + memcpy(buf, bitdata + *offset, rdsize); + *offset += rdsize; +} + +static void readinfo_bitstream(char *bitdata, char *buf, int *offset) +{ + char tbuf[64]; + int32_t len; + + /* read section char */ + read_bitstream(bitdata, tbuf, offset, 1); + + /* read length */ + read_bitstream(bitdata, tbuf, offset, 2); + + len = tbuf[0] << 8 | tbuf[1]; + + read_bitstream(bitdata, buf, offset, len); + buf[len] = '\0'; +} + +/* + * read bitdata length + */ +static int readlength_bitstream(char *bitdata, int *lendata, int *offset) +{ + char tbuf[64]; + + /* read section char */ + read_bitstream(bitdata, tbuf, offset, 1); + + /* make sure it is section 'e' */ + if (tbuf[0] != 'e') { + pr_err("error: length section is not 'e', but %c\n", tbuf[0]); + return -1; + } + + /* read 4bytes length */ + read_bitstream(bitdata, tbuf, offset, 4); + + *lendata = tbuf[0] << 24 | tbuf[1] << 16 | + tbuf[2] << 8 | tbuf[3]; + + return 0; +} + + +/* + * read first 13 bytes to check bitstream magic number + */ +static int readmagic_bitstream(char *bitdata, int *offset) +{ + char buf[13]; + int r; + + read_bitstream(bitdata, buf, offset, 13); + r = memcmp(buf, bits_magic, 13); + if (r) { + pr_err("error: corrupted header"); + return -1; + } + pr_info("bitstream file magic number Ok\n"); + + *offset = 13; /* magic length */ + + return 0; +} + +/* + * NOTE: supports only bitstream format + */ +static enum fmt_image get_imageformat(struct fpgaimage *fimage) +{ + return f_bit; +} + +static void gs_print_header(struct fpgaimage *fimage) +{ + pr_info("file: %s\n", fimage->filename); + pr_info("part: %s\n", fimage->part); + pr_info("date: %s\n", fimage->date); + pr_info("time: %s\n", fimage->time); + pr_info("lendata: %d\n", fimage->lendata); +} + +static void gs_read_bitstream(struct fpgaimage *fimage) +{ + char *bitdata; + int size; + int offset; + + offset = 0; + bitdata = (char *)fimage->fw_entry->data; + size = fimage->fw_entry->size; + + readmagic_bitstream(bitdata, &offset); + readinfo_bitstream(bitdata, fimage->filename, &offset); + readinfo_bitstream(bitdata, fimage->part, &offset); + readinfo_bitstream(bitdata, fimage->date, &offset); + readinfo_bitstream(bitdata, fimage->time, &offset); + readlength_bitstream(bitdata, &fimage->lendata, &offset); + + fimage->fpgadata = bitdata + offset; +} + +static int gs_read_image(struct fpgaimage *fimage) +{ + int img_fmt; + + img_fmt = get_imageformat(fimage); + + switch (img_fmt) { + case f_bit: + pr_info("image is bitstream format\n"); + gs_read_bitstream(fimage); + break; + default: + pr_err("unsupported fpga image format\n"); + return -1; + }; + + gs_print_header(fimage); + + return 0; +} + +static int gs_load_image(struct fpgaimage *fimage, char *file) +{ + int err; + + pr_info("load fpgaimage %s\n", file); + + err = request_firmware(&fimage->fw_entry, file, fpga_device); + if (err != 0) { + pr_err("firmware %s is missing, cannot continue.\n", file); + return err; + } + + return 0; +} + +static int gs_download_image(struct fpgaimage *fimage, enum wbus bus_bytes) +{ + char *bitdata; + int size, i, cnt; + cnt = 0; + + bitdata = (char *)fimage->fpgadata; + size = fimage->lendata; + +#ifdef DEBUG_FPGA + datadump("bitfile sample", bitdata, 0x100); +#endif /* DEBUG_FPGA */ + + if (!xl_supported_prog_bus_width(bus_bytes)) { + pr_err("unsupported program bus width %d\n", + bus_bytes); + return -1; + } + + /* Bring csi_b, rdwr_b Low and program_b High */ + xl_program_b(1); + xl_rdwr_b(0); + xl_csi_b(0); + + /* Configuration reset */ + xl_program_b(0); + msleep(20); + xl_program_b(1); + + /* Wait for Device Initialization */ + while (xl_get_init_b() == 0) + ; + + pr_info("device init done\n"); + + for (i = 0; i < size; i += bus_bytes) + xl_shift_bytes_out(bus_bytes, bitdata+i); + + pr_info("program done\n"); + + /* Check INIT_B */ + if (xl_get_init_b() == 0) { + pr_err("init_b 0\n"); + return -1; + } + + while (xl_get_done_b() == 0) { + if (cnt++ > MAX_WAIT_DONE) { + pr_err("init_B %d\n", xl_get_init_b()); + break; + } + } + + if (cnt > MAX_WAIT_DONE) { + pr_err("fpga download fail\n"); + return -1; + } + + pr_info("download fpgaimage\n"); + + /* Compensate for Special Startup Conditions */ + xl_shift_cclk(8); + + return 0; +} + +static int gs_release_image(struct fpgaimage *fimage) +{ + release_firmware(fimage->fw_entry); + pr_info("release fpgaimage\n"); + + return 0; +} + +/* + * NOTE: supports systemmap parallel programming + */ +static int gs_set_download_method(struct fpgaimage *fimage) +{ + pr_info("set program method\n"); + + fimage->dmethod = m_systemmap; + + pr_info("systemmap program method\n"); + + return 0; +} + +static int gs_fpgaboot_release(struct inode *inode, struct file *file) +{ + pr_info("gs_fpgaboot_release\n"); + return 0; +} + +static int gs_fpgaboot_open(struct inode *inode, struct file *file) +{ + pr_info("gs_fpgaboot_open\n"); + return 0; +} + +static ssize_t gs_fpgaboot_write(struct file *f, + const char *c, size_t s, loff_t *lo) +{ + pr_info("gs_fpgaboot_write\n"); + return 0; +} + +const struct file_operations fpga_fops = { + .owner = THIS_MODULE, + .open = gs_fpgaboot_open, + .write = gs_fpgaboot_write, + .release = gs_fpgaboot_release, +}; + +static int init_driver(void) +{ + int retval; + + /* + * First, see if we can dynamically allocate + * a major for our device + */ + fpga_major = register_chrdev(0, DEVICE_NAME, &fpga_fops); + if (fpga_major < 0) { + pr_err("failed to register device: error %d\n", + fpga_major); + retval = fpga_major; + goto failed_chrdevreg; + } + + /* + * We can either tie our device to + * a bus (existing, or one that we create) + * or use a "virtual" device class. + * For this example, we choose the latter + */ + fpga_class = class_create(THIS_MODULE, CLASS_NAME); + if (IS_ERR(fpga_class)) { + pr_err("failed to register device class '%s'\n", + CLASS_NAME); + retval = PTR_ERR(fpga_class); + goto failed_classreg; + } + + /* + * With a class, the easiest way to instantiate + * a device is to call device_create() + */ + fpga_device = device_create(fpga_class, NULL, + MKDEV(fpga_major, 0), NULL, + CLASS_NAME "_" DEVICE_NAME); + if (IS_ERR(fpga_device)) { + pr_err("failed to create device '%s_%s'\n", + CLASS_NAME, DEVICE_NAME); + retval = PTR_ERR(fpga_device); + goto failed_devreg; + } + + return 0; + +failed_devreg: + class_unregister(fpga_class); + class_destroy(fpga_class); +failed_classreg: + unregister_chrdev(fpga_major, DEVICE_NAME); +failed_chrdevreg: + return -1; +} + +static void finish_driver(void) +{ + device_destroy(fpga_class, MKDEV(fpga_major, 0)); + class_unregister(fpga_class); + class_destroy(fpga_class); + unregister_chrdev(fpga_major, DEVICE_NAME); +} + +static int gs_fpgaboot(void) +{ + int err; + struct fpgaimage *fimage; + + fimage = kmalloc(sizeof(struct fpgaimage), GFP_KERNEL); + if (fimage == NULL) { + pr_err("No memory is available\n"); + goto err_out; + } + + err = gs_load_image(fimage, file); + if (err) { + pr_err("gs_load_image error\n"); + goto err_out1; + } + + err = gs_read_image(fimage); + if (err) { + pr_err("gs_read_image error\n"); + goto err_out2; + } + + err = gs_set_download_method(fimage); + if (err) { + pr_err("gs_set_download_method error\n"); + goto err_out2; + } + + /* TODO: get bus width input instead of hardcoded */ + err = gs_download_image(fimage, bus_2byte); + if (err) { + pr_err("gs_download_image error\n"); + goto err_out2; + } + + err = gs_release_image(fimage); + if (err) { + pr_err("gs_release_image error\n"); + goto err_out1; + } + + kfree(fimage); + return 0; + +err_out2: + err = gs_release_image(fimage); + if (err) + pr_err("gs_release_image error\n"); +err_out1: + kfree(fimage); + +err_out: + return -1; + +} + +static int __init gs_fpgaboot_init(void) +{ + int err, r; + + r = -1; + + pr_info("FPGA DOWNLOAD --->\n"); + pr_info("built at %s UTC\n", __TIMESTAMP__); + + pr_info("FPGA image file name: %s\n", file); + + err = init_driver(); + if (err != 0) { + pr_err("FPGA DRIVER INIT FAIL!!\n"); + return r; + } + + err = xl_init_io(); + if (err) { + pr_err("GPIO INIT FAIL!!\n"); + r = -1; + goto errout; + } + + err = gs_fpgaboot(); + if (err) { + pr_err("FPGA DOWNLOAD FAIL!!\n"); + r = -1; + goto errout; + } + + pr_info("FPGA DOWNLOAD DONE <---\n"); + + r = 0; + return r; + +errout: + finish_driver(); + + return r; +} + +static void __exit gs_fpgaboot_exit(void) +{ + finish_driver(); + pr_info("FPGA image download module removed\n"); +} + +module_init(gs_fpgaboot_init); +module_exit(gs_fpgaboot_exit); + +MODULE_AUTHOR("Insop Song"); +MODULE_DESCRIPTION("Xlinix FPGA bitstream image download"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/gs_fpgaboot/gs_fpgaboot.h b/drivers/staging/gs_fpgaboot/gs_fpgaboot.h new file mode 100644 index 0000000..f41f4cc --- /dev/null +++ b/drivers/staging/gs_fpgaboot/gs_fpgaboot.h @@ -0,0 +1,56 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/firmware.h> + +#define MAX_STR 256 + +enum fmt_image { + f_bit, /* only bitstream is supported */ + f_rbt, + f_bin, + f_mcs, + f_hex, +}; + +enum mdownload { + m_systemmap, /* only system map is supported */ + m_serial, + m_jtag, +}; + +/* + * xilinx fpgaimage information + * NOTE: use MAX_STR instead of dynamic alloc for simplicity + */ +struct fpgaimage { + enum fmt_image fmt_img; + enum mdownload dmethod; + + const struct firmware *fw_entry; + + /* + * the followings can be read from bitstream, + * but other image format should have as well + */ + char filename[MAX_STR]; + char part[MAX_STR]; + char date[MAX_STR]; + char time[MAX_STR]; + int32_t lendata; + char *fpgadata; +}; diff --git a/drivers/staging/gs_fpgaboot/io.c b/drivers/staging/gs_fpgaboot/io.c new file mode 100644 index 0000000..079e8a0 --- /dev/null +++ b/drivers/staging/gs_fpgaboot/io.c @@ -0,0 +1,331 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/fs.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#include <include/asm/io.h> +#include <linux/firmware.h> + +#include "io.h" + +/* + * this should come from board specific configuration + */ +#define CONFIG_B4860G100 + +#ifdef CONFIG_B4860G100 +static struct gpiobus gbus; +#endif /* CONFIG_B4860G100 */ + +static inline void byte0_out(unsigned char data); +static inline void byte1_out(unsigned char data); +static inline void xl_cclk_b(int32_t i); + + +/* Assert and Deassert CCLK */ +void xl_shift_cclk(int count) +{ + int i; + for (i = 0; i < count; i++) { + xl_cclk_b(1); + xl_cclk_b(0); + } +} +EXPORT_SYMBOL(xl_shift_cclk); + +int xl_supported_prog_bus_width(enum wbus bus_bytes) +{ + switch (bus_bytes) { + case bus_1byte: + break; + case bus_2byte: + break; + default: + pr_err("unsupported program bus width %d\n", + bus_bytes); + return 0; + } + + return 1; +} +EXPORT_SYMBOL(xl_supported_prog_bus_width); + +/* Serialize byte and clock each bit on target's DIN and CCLK pins */ +void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata) +{ + /* + * supports 1 and 2 bytes programming mode + */ + if (likely(bus_byte == bus_2byte)) + byte0_out(pdata[0]); + + byte1_out(pdata[1]); + xl_shift_cclk(1); +} +EXPORT_SYMBOL(xl_shift_bytes_out); + +/* + * generic bit swap for xilinx SYSTEMMAP FPGA programming + */ +static inline unsigned char bitswap(unsigned char s) +{ + unsigned char d; + d = (((s&0x80)>>7) | ((s&0x40)>>5) | ((s&0x20)>>3) | ((s&0x10)>>1) | + ((s&0x08)<<1) | ((s&0x04)<<3) | ((s&0x02)<<5) | ((s&0x01)<<7)); + return d; +} + +#ifdef CONFIG_B4860G100 +/* + * ====================================================================== + * board specific configuration + */ + +static inline void mpc85xx_gpio_set_dir( + int32_t port, + uint32_t mask, + uint32_t dir) +{ + dir |= (in_be32(gbus.r[port]+GPDIR) & ~mask); + out_be32(gbus.r[port]+GPDIR, dir); +} + +static inline void mpc85xx_gpio_set(int32_t port, uint32_t mask, uint32_t val) +{ + /* First mask off the unwanted parts of "dir" and "val" */ + val &= mask; + + /* Now read in the values we're supposed to preserve */ + val |= (in_be32(gbus.r[port]+GPDAT) & ~mask); + + out_be32(gbus.r[port]+GPDAT, val); +} + +static inline uint32_t mpc85xx_gpio_get(int32_t port, uint32_t mask) +{ + /* Read the requested values */ + return in_be32(gbus.r[port]+GPDAT) & mask; +} + +static inline void mpc85xx_gpio_set_low(int32_t port, uint32_t gpios) +{ + mpc85xx_gpio_set(port, gpios, 0x00000000); +} + +static inline void mpc85xx_gpio_set_high(int32_t port, uint32_t gpios) +{ + mpc85xx_gpio_set(port, gpios, 0xFFFFFFFF); +} + +static inline void gpio_set_value(int32_t port, uint32_t gpio, uint32_t value) +{ + int32_t g; + g = 31 - gpio; + if (value) + mpc85xx_gpio_set_high(port, 1U << g); + else + mpc85xx_gpio_set_low(port, 1U << g); +} + +static inline int gpio_get_value(int32_t port, uint32_t gpio) +{ + int32_t g; + g = 31 - gpio; + return !!mpc85xx_gpio_get(port, 1U << g); +} + +static inline void xl_cclk_b(int32_t i) +{ + gpio_set_value(XL_CCLK_PORT, XL_CCLK_PIN, i); +} + +void xl_program_b(int32_t i) +{ + gpio_set_value(XL_PROGN_PORT, XL_PROGN_PIN, i); +} +EXPORT_SYMBOL(xl_program_b); + +void xl_rdwr_b(int32_t i) +{ + gpio_set_value(XL_RDWRN_PORT, XL_RDWRN_PIN, i); +} +EXPORT_SYMBOL(xl_rdwr_b); + +void xl_csi_b(int32_t i) +{ + gpio_set_value(XL_CSIN_PORT, XL_CSIN_PIN, i); +} +EXPORT_SYMBOL(xl_csi_b); + +int xl_get_init_b(void) +{ + return gpio_get_value(XL_INITN_PORT, XL_INITN_PIN); +} +EXPORT_SYMBOL(xl_get_init_b); + +int xl_get_done_b(void) +{ + return gpio_get_value(XL_DONE_PORT, XL_DONE_PIN); +} +EXPORT_SYMBOL(xl_get_done_b); + + +/* G100 specific bit swap and remmap (to gpio pins) for byte 0 */ +static inline uint32_t bit_remap_byte0(uint32_t s) +{ + uint32_t d; + d = (((s&0x80)>>7) | ((s&0x40)>>5) | ((s&0x20)>>3) | ((s&0x10)>>1) | + ((s&0x08)<<1) | ((s&0x04)<<3) | ((s&0x02)<<6) | ((s&0x01)<<9)); + return d; +} + +/* + * G100 specific MSB, in this order [byte0 | byte1], out + */ +static inline void byte0_out(unsigned char data) +{ + uint32_t swap32; + swap32 = bit_remap_byte0((uint32_t) data) << 8; + + mpc85xx_gpio_set(0, 0x0002BF00, (uint32_t) swap32); +} + +/* + * G100 specific LSB, in this order [byte0 | byte1], out + */ +static inline void byte1_out(unsigned char data) +{ + mpc85xx_gpio_set(0, 0x000000FF, (uint32_t) bitswap(data)); +} + +/* + * TODO: + * - configurable per device type for different I/O config + * so that this can be easily extended to G200 and more + * + * - have a device specific data struct (config, and func ptrs) + * + * - read device identity and use that setting i/o config + * + */ +int xl_init_io() +{ + struct device_node *np; + const u32 *p_reg; + int reg, cnt; + + cnt = 0; + memset(&gbus, 0, sizeof(struct gpiobus)); + for_each_compatible_node(np, NULL, "fsl,qoriq-gpio") { + p_reg = of_get_property(np, "reg", NULL); + if (p_reg == NULL) + break; + reg = (int) *p_reg; + gbus.r[cnt] = of_iomap(np, 0); + + if (!gbus.r[cnt]) { + pr_err("not findding gpio cell-index %d\n", cnt); + return -ENODEV; + } + cnt++; + } + mpc85xx_gpio_set_dir(0, 0x0002BFFF, 0x0002BFFF); + mpc85xx_gpio_set_dir(1, 0x00240060, 0x00240060); + + gbus.ngpio = cnt; + + return 0; +} +EXPORT_SYMBOL(xl_init_io); + + +#else /* placeholder for boards with different config */ + +void xl_program_b(int32_t i) +{ + return; +} +EXPORT_SYMBOL(xl_program_b); + +void xl_rdwr_b(int32_t i) +{ + return; +} +EXPORT_SYMBOL(xl_rdwr_b); + +void xl_csi_b(int32_t i) +{ + return; +} +EXPORT_SYMBOL(xl_csi_b); + +int xl_get_init_b(void) +{ + return -1; +} +EXPORT_SYMBOL(xl_get_init_b); + +int xl_get_done_b(void) +{ + return -1; +} +EXPORT_SYMBOL(xl_get_done_b); + + +/* G100 specific bit swap and remmap (to gpio pins) for byte 0 */ +static inline uint32_t bit_remap_byte0(uint32_t s) +{ + return -1; +} + +static inline void byte0_out(unsigned char data) +{ + return; +} + +static inline void byte1_out(unsigned char data) +{ + return; +} + +static inline void xl_cclk_b(int32_t i) +{ + return; +} + +/* + * - configurable per device type for different I/O config + * so that this can be easily extended to G200 and more + * + */ +int xl_init_io() +{ + return -1; +} +EXPORT_SYMBOL(xl_init_io); + +#endif /* CONFIG_B4860G100 */ diff --git a/drivers/staging/gs_fpgaboot/io.h b/drivers/staging/gs_fpgaboot/io.h new file mode 100644 index 0000000..7b46ac2 --- /dev/null +++ b/drivers/staging/gs_fpgaboot/io.h @@ -0,0 +1,90 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#define GPDIR 0 +#define GPCFG 4 /* open drain or not */ +#define GPDAT 8 + +/* + * gpio port and pin definitions + * NOTE: port number starts from 0 + */ +#define XL_INITN_PORT 1 +#define XL_INITN_PIN 14 +#define XL_RDWRN_PORT 1 +#define XL_RDWRN_PIN 13 +#define XL_CCLK_PORT 1 +#define XL_CCLK_PIN 10 +#define XL_PROGN_PORT 1 +#define XL_PROGN_PIN 25 +#define XL_CSIN_PORT 1 +#define XL_CSIN_PIN 26 +#define XL_DONE_PORT 1 +#define XL_DONE_PIN 27 + +/* + * gpio mapping + * + XL_config_D0 – gpio1_31 + Xl_config_d1 – gpio1_30 + Xl_config_d2 – gpio1_29 + Xl_config_d3 – gpio1_28 + Xl_config_d4 – gpio1_27 + Xl_config_d5 – gpio1_26 + Xl_config_d6 – gpio1_25 + Xl_config_d7 – gpio1_24 + Xl_config_d8 – gpio1_23 + Xl_config_d9 – gpio1_22 + Xl_config_d10 – gpio1_21 + Xl_config_d11 – gpio1_20 + Xl_config_d12 – gpio1_19 + Xl_config_d13 – gpio1_18 + Xl_config_d14 – gpio1_16 + Xl_config_d15 – gpio1_14 +* +*/ + +/* + * program bus width in bytes + */ +enum wbus { + bus_1byte = 1, + bus_2byte = 2, +}; + + +#define MAX_WAIT_DONE 10000 + + +struct gpiobus { + int ngpio; + void __iomem *r[4]; +}; + +int xl_supported_prog_bus_width(enum wbus bus_bytes); + +void xl_program_b(int32_t i); +void xl_rdwr_b(int32_t i); +void xl_csi_b(int32_t i); + +int xl_get_init_b(void); +int xl_get_done_b(void); + +void xl_shift_cclk(int count); +void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata); + +int xl_init_io(void); -- 1.7.9.5 _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
