Hello, I'm in the process of trying to debug an issue with a VME A/D board and have noticed some curious behavior in the VME bus protocol. We are using the vme_tsi148 bridge driver along with the vme_user driver to access the VME boards. The A/D board requires D32 bus cycles and the VME master window is configured accordingly, however, when monitoring the bus cycles with a logic analyzer, we noticed that the CPU is transferring one byte at a time (i.e. four D8 transfers rather than one D32). Is this the expected behavior of the tsi148 driver? If there is a more appropriate mailing-list for this question, please let me know. Thanks. --Mike ----------------------------------------------------------------------------- Michael Kenney Ocean Engineering Dept Applied Physics Lab University of Washington ----------------------------------------------------------------------------- _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
