This patch removes these sparse warnings found in the cls.c file:
warning: incorrect type in argument 1 (different address spaces)
expected void const volatile [noderef] <asn:2>*addr
got unsigned char volatile *<noident>
warning: incorrect type in argument 2 (different address spaces)
expected void volatile [noderef] <asn:2>*addr
got unsigned char volatile *<noident>
The variables passed to readb and writeb need to
be of type u8 with a __iomem marker. These warnings
were popping up everytime the readb and writeb
functions were called with a cls_uart_struct variable.
The change made to the driver.h file adds the marker
to the cls_uart_struct and the changes in cls.h
changes its variables' types.
Signed-off-by: Lidza Louina <lidza.louina@xxxxxxxxx>
---
drivers/staging/dgnc/dgnc_cls.h | 16 ++++++++--------
drivers/staging/dgnc/dgnc_driver.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/dgnc/dgnc_cls.h b/drivers/staging/dgnc/dgnc_cls.h
index a273385..ffe8535 100644
--- a/drivers/staging/dgnc/dgnc_cls.h
+++ b/drivers/staging/dgnc/dgnc_cls.h
@@ -36,14 +36,14 @@
************************************************************************/
struct cls_uart_struct {
- volatile uchar txrx; /* WR RHR/THR - Holding Reg */
- volatile uchar ier; /* WR IER - Interrupt Enable Reg */
- volatile uchar isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
- volatile uchar lcr; /* WR LCR - Line Control Reg */
- volatile uchar mcr; /* WR MCR - Modem Control Reg */
- volatile uchar lsr; /* WR LSR - Line Status Reg */
- volatile uchar msr; /* WR MSR - Modem Status Reg */
- volatile uchar spr; /* WR SPR - Scratch Pad Reg */
+ u8 txrx; /* WR RHR/THR - Holding Reg */
+ u8 ier; /* WR IER - Interrupt Enable Reg */
+ u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
+ u8 lcr; /* WR LCR - Line Control Reg */
+ u8 mcr; /* WR MCR - Modem Control Reg */
+ u8 lsr; /* WR LSR - Line Status Reg */
+ u8 msr; /* WR MSR - Modem Status Reg */
+ u8 spr; /* WR SPR - Scratch Pad Reg */
};
/* Where to read the interrupt register (8bits) */
diff --git a/drivers/staging/dgnc/dgnc_driver.h b/drivers/staging/dgnc/dgnc_driver.h
index 47bc781..6644e95 100644
--- a/drivers/staging/dgnc/dgnc_driver.h
+++ b/drivers/staging/dgnc/dgnc_driver.h
@@ -481,7 +481,7 @@ struct channel_t {
uchar ch_mistat; /* FEP input modem status */
struct neo_uart_struct *ch_neo_uart; /* Pointer to the "mapped" UART struct */
- struct cls_uart_struct *ch_cls_uart; /* Pointer to the "mapped" UART struct */
+ struct cls_uart_struct __iomem *ch_cls_uart; /* Pointer to the "mapped" UART struct */
uchar ch_cached_lsr; /* Cached value of the LSR register */
--
1.8.1.2
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